Inventor
LOUBET NICOLAS J
US55 patents
Patents
50 patentsUS10074575B1Sep 11, 2018
Integrating and isolating nFET and pFET nanosheet transistors on a substrate
IBM45 citations98
US9755017B1Sep 5, 2017
Co-integration of silicon and silicon-germanium channels for nanosheet devices
IBM48 citations98
US9761722B1Sep 12, 2017
Isolation of bulk FET devices with embedded stressors
IBM25 citations94
US9741626B1Aug 22, 2017
Vertical transistor with uniform bottom spacer formed by selective oxidation
IBM47 citations94
US10566445B2Feb 18, 2020
Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates
IBM11 citations86
US10971490B2Apr 6, 2021
Three-dimensional field effect device
IBM6 citations84
US10741660B2Aug 11, 2020
Nanosheet single gate (SG) and extra gate (EG) field effect transistor (FET) co-integration
IBM9 citations84
US10367062B2Jul 30, 2019
Co-integration of silicon and silicon-germanium channels for nanosheet devices
IBM4 citations84
US10304936B2May 28, 2019
Protection of high-K dielectric during reliability anneal on nanosheet structures
IBM5 citations84
US10249739B2Apr 2, 2019
Nanosheet MOSFET with partial release and source/drain epitaxy
IBM9 citations84
US10242920B2Mar 26, 2019
Integrating and isolating NFET and PFET nanosheet transistors on a substrate
IBM7 citations84
US10177226B2Jan 8, 2019
Preventing threshold voltage variability in stacked nanosheets
IBM5 citations84
US10020398B1Jul 10, 2018
Stress induction in 3D device channel using elastic relaxation of high stress material
IBM12 citations84
US9761699B2Sep 12, 2017
Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
IBM5 citations84
US9735062B1Aug 15, 2017
Defect reduction in channel silicon germanium on patterned silicon
IBM9 citations84
US9716086B1Jul 25, 2017
Method and structure for forming buried ESD with FinFETs
IBM7 citations84
US9679780B1Jun 13, 2017
Polysilicon residue removal in nanosheet MOSFETs
IBM11 citations84
US9978678B1May 22, 2018
Vertically integrated nanosheet fuse
IBM5 citations83
US11222981B2Jan 11, 2022
Three-dimensional field effect device
IBM1 citations73
US10930756B2Feb 23, 2021
Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates
IBM2 citations73
US10692985B2Jun 23, 2020
Protection of high-K dielectric during reliability anneal on nanosheet structures
IBM2 citations73
US10658493B2May 19, 2020
Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates
IBM3 citations73
US10541272B2Jan 21, 2020
Steep-switch vertical field effect transistor
IBM2 citations73
US10541335B2Jan 21, 2020
Stress induction in 3D device channel using elastic relaxation of high stress material
IBM1 citations73
US10490667B1Nov 26, 2019
Three-dimensional field effect device
IBM2 citations73
US10446670B2Oct 15, 2019
Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures
IBM2 citations73
US10396185B2Aug 27, 2019
Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
IBM2 citations73
US10340340B2Jul 2, 2019
Multiple-threshold nanosheet transistors
IBM3 citations73
US10026810B2Jul 17, 2018
Co-integration of silicon and silicon-germanium channels for nanosheet devices
IBM3 citations73
US9941355B1Apr 10, 2018
Co-integration of elastic and plastic relaxation on the same wafer
IBM3 citations73
US9842929B1Dec 12, 2017
Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate
IBM4 citations73
US9859426B1Jan 2, 2018
Semiconductor device including optimized elastic strain buffer
IBM2 citations72
US10896816B2Jan 19, 2021
Silicon residue removal in nanosheet transistors
IBM4 citations71
US12237325B2Feb 25, 2025
Three-dimensional field effect device
IBM0 citations63
US11817502B2Nov 14, 2023
Three-dimensional field effect device
IBM0 citations63
US11183593B2Nov 23, 2021
Three-dimensional field effect device
IBM0 citations63
US11094823B2Aug 17, 2021
Stress induction in 3D device channel using elastic relaxation of high stress material
IBM0 citations63
US11088026B2Aug 10, 2021
Wimpy device by selective laser annealing
IBM0 citations63
US11069744B2Jul 20, 2021
Steep-switch vertical field effect transistor
IBM0 citations63
US10998441B2May 4, 2021
Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate
IBM0 citations63
US10043748B1Aug 7, 2018
Vertically integrated nanosheet fuse
IBM1 citations61
US10734504B2Aug 4, 2020
Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
IBM0 citations52
US10644110B2May 5, 2020
Co-integration of elastic and plastic relaxation on the same wafer
IBM0 citations52
US10580858B2Mar 3, 2020
Preventing threshold voltage variability in stacked nanosheets
IBM0 citations52
US10566240B2Feb 18, 2020
Wimpy device by selective laser annealing
IBM0 citations52
US10297665B2May 21, 2019
Co-integration of elastic and plastic relaxation on the same wafer
IBM0 citations52
US10262900B2Apr 16, 2019
Wimpy device by selective laser annealing
IBM0 citations52
US10170552B2Jan 1, 2019
Co-integration of silicon and silicon-germanium channels for nanosheet devices
IBM0 citations52
US9997352B2Jun 12, 2018
Polysilicon residue removal in nanosheet MOSFETs
IBM1 citations52
US9991166B2Jun 5, 2018
Wimpy device by selective laser annealing
IBM0 citations52
Showing the top 50 of 55 patents by PatentIndex Score.