Inventor
HANKINS RICHARD
US26 patents
⚠️ This page may combine multiple inventors who share the name “HANKINS RICHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PURE STORAGE INC
15 patentsUS10838834B1Nov 17, 2020
Managing read and write requests targeting a failed storage region in a storage system
PURE STORAGE INC13 citations94
US10346043B2Jul 9, 2019
Adaptive computing for data compression
PURE STORAGE INC29 citations94
US10248516B1Apr 2, 2019
Processing read and write requests during reconstruction in a storage system
PURE STORAGE INC17 citations94
US9588842B1Mar 7, 2017
Drive rebuild
PURE STORAGE INC16 citations92
US9977600B1May 22, 2018
Optimizing flattening in a multi-level data structure
PURE STORAGE INC6 citations84
US9727485B1Aug 8, 2017
Metadata rewrite and flatten optimization
PURE STORAGE INC6 citations84
US10254964B1Apr 9, 2019
Managing mapping information in a storage system
PURE STORAGE INC1 citations73
US9864769B2Jan 9, 2018
Storing data utilizing repeating pattern detection
PURE STORAGE INC3 citations73
US11169817B1Nov 9, 2021
Optimizing a boot sequence in a storage system
PURE STORAGE INC2 citations71
US10474363B1Nov 12, 2019
Space reporting in a storage system
PURE STORAGE INC5 citations71
US10296354B1May 21, 2019
Optimized boot operations within a flash storage array
PURE STORAGE INC3 citations71
US11662909B2May 30, 2023
Metadata management in a storage system
PURE STORAGE INC0 citations62
US11561949B1Jan 24, 2023
Reconstructing deduplicated data
PURE STORAGE INC0 citations62
US11281375B1Mar 22, 2022
Optimizing for data reduction in a storage system
PURE STORAGE INC0 citations62
US10783131B1Sep 22, 2020
Deduplicating patterned data in a storage system
PURE STORAGE INC0 citations52
INTEL CORP
7 patentsUS9990206B2Jun 5, 2018
Mechanism for instruction set based thread execution of a plurality of instruction sequencers
INTEL CORP8 citations82
US8028295B2Sep 27, 2011
Apparatus, system, and method for persistent user-level thread
INTEL CORP4 citations74
US9459874B2Oct 4, 2016
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
INTEL CORP1 citations62
US9875102B2Jan 23, 2018
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9766891B2Sep 19, 2017
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9588771B2Mar 7, 2017
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
INTEL CORP1 citations52
US9383997B2Jul 5, 2016
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52