Inventor
KOUNAVIS MICHAEL
US31 patents
⚠️ This page may combine multiple inventors who share the name “KOUNAVIS MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS7590930B2Sep 15, 2009
Instructions for performing modulo-2 multiplication and bit reflection
INTEL CORP22 citations92
US7646779B2Jan 12, 2010
Hierarchical packet scheduler using hole-filling and multiple packet buffering
INTEL CORP14 citations84
US7457296B2Nov 25, 2008
Method and apparatus for sorting packets in packet schedulers using a connected trie data structure
INTEL CORP17 citations84
US9536136B2Jan 3, 2017
Multi-layer skin detection and fused hand pose matching
INTEL CORP9 citations82
US11469902B2Oct 11, 2022
Systems and methods of using cryptographic primitives for error location, correction, and device recovery
INTEL CORP3 citations73
US11444748B2Sep 13, 2022
Ultra-low latency advanced encryption standard
INTEL CORP3 citations73
US10498865B2Dec 3, 2019
Security-oriented compression
INTEL CORP3 citations71
US10291394B2May 14, 2019
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP0 citations63
US7886214B2Feb 8, 2011
Determining a message residue
INTEL CORP4 citations63
US7525962B2Apr 28, 2009
Reducing memory access bandwidth consumption in a hierarchical packet scheduler
INTEL CORP6 citations63
US11895221B2Feb 6, 2024
Ultra-low latency advanced encryption standard
INTEL CORP0 citations62
US11496486B2Nov 8, 2022
Methods and apparatus to support reliable digital communications without integrity metadata
INTEL CORP0 citations62
US11082432B2Aug 3, 2021
Methods and apparatus to support reliable digital communications without integrity metadata
INTEL CORP0 citations62
US11568211B2Jan 31, 2023
Defending neural networks by randomizing model weights
INTEL CORP1 citations61
US10949358B2Mar 16, 2021
Secure address translation services using message authentication codes and invalidation tracking
INTEL CORP1 citations61
US12135643B2Nov 5, 2024
Sequestered memory for selective storage of metadata corresponding to cached data
INTEL CORP0 citations52
US7707483B2Apr 27, 2010
Technique for performing cyclic redundancy code error detection
INTEL CORP0 citations52
US10929527B2Feb 23, 2021
Methods and arrangements for implicit integrity
INTEL CORP0 citations51
US10855815B2Dec 1, 2020
Security-oriented compression
INTEL CORP0 citations50
US10757227B2Aug 25, 2020
Security-oriented compression
INTEL CORP0 citations50
US11657162B2May 23, 2023
Adversarial training of neural networks using information about activation path differentials
INTEL CORP0 citations47
US10672401B2Jun 2, 2020
Speech and video dual mode gaussian mixture model scoring accelerator
INTEL CORP0 citations47
US9390320B2Jul 12, 2016
Performing hand gesture recognition using 2D image data
INTEL CORP1 citations47
US10755386B2Aug 25, 2020
Median filtering of images using directed search
INTEL CORP0 citations41
US10496876B2Dec 3, 2019
Specular light shadow removal for image de-noising
INTEL CORP0 citations41
US9558389B2Jan 31, 2017
Reliable fingertip and palm detection
INTEL CORP0 citations41
GUERON SHAY
3 patentsUS8340280B2Dec 25, 2012
Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations
GUERON SHAY46 citations94
US8144864B2Mar 27, 2012
Method for speeding up the computations for characteristic 2 elliptic curve cryptographic systems
GUERON SHAY2 citations63
US8442217B2May 14, 2013
Method of implementing one way hash functions and apparatus therefor
GUERON SHAY1 citations52