Inventor
WASKIEWICZ CHRISTOPHER J
US52 patents
Patents
50 patentsUS9666528B1May 30, 2017
BEOL vertical fuse formed over air gap
IBM430 citations99
US9449871B1Sep 20, 2016
Hybrid airgap structure with oxide liner
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US6294449B1Sep 25, 2001
Self-aligned contact for closely spaced transistors
IBM37 citations92
US10361129B1Jul 23, 2019
Self-aligned double patterning formed fincut
IBM14 citations86
US10770653B1Sep 8, 2020
Selective dielectric deposition to prevent gouging in MRAM
IBM7 citations84
US10483361B1Nov 19, 2019
Wrap-around-contact structure for top source/drain in vertical FETs
IBM11 citations84
US9780027B2Oct 3, 2017
Hybrid airgap structure with oxide liner
IBM13 citations84
US8987133B2Mar 24, 2015
Titanium oxynitride hard mask for lithographic patterning
IBM9 citations84
US11171051B1Nov 9, 2021
Contacts and liners having multi-segmented protective caps
IBM9 citations83
US8986921B2Mar 24, 2015
Lithographic material stack including a metal-compound hard mask
IBM11 citations81
US11495538B2Nov 8, 2022
Fully aligned via for interconnect
IBM3 citations73
US11476346B2Oct 18, 2022
Vertical transistor having an oxygen-blocking top spacer
IBM2 citations73
US11244861B2Feb 8, 2022
Method and structure for forming fully-aligned via
IBM2 citations73
US11239165B2Feb 1, 2022
Method of forming an interconnect structure with enhanced corner connection
IBM2 citations73
US11152265B2Oct 19, 2021
Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors
IBM2 citations73
US10741652B2Aug 11, 2020
Wrap-around-contact structure for top source/drain in vertical FETs
IBM2 citations73
US6303275B1Oct 16, 2001
Method for resist filling and planarization of high aspect ratio features
IBM7 citations72
US12009422B2Jun 11, 2024
Self aligned top contact for vertical transistor
IBM0 citations63
US11901440B2Feb 13, 2024
Sacrificial fin for self-aligned contact rail formation
IBM0 citations63
US11876124B2Jan 16, 2024
Vertical transistor having an oxygen-blocking layer
IBM0 citations63
US11742246B2Aug 29, 2023
Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors
IBM0 citations63
US11742354B2Aug 29, 2023
Top epitaxial layer and contact for VTFET
IBM0 citations63
US11646358B2May 9, 2023
Sacrificial fin for contact self-alignment
IBM0 citations63
US11316029B2Apr 26, 2022
Sacrificial fin for contact self-alignment
IBM0 citations63
US11211291B2Dec 28, 2021
Via formation with robust hardmask removal
IBM0 citations63
US10985025B2Apr 20, 2021
Fin cut profile using fin base liner
IBM0 citations63
US10892336B2Jan 12, 2021
Wrap-around-contact structure for top source/drain in vertical FETS
IBM0 citations63
US9087876B2Jul 21, 2015
Titanium oxynitride hard mask for lithographic patterning
IBM3 citations63
US12464809B2Nov 4, 2025
Vertical field effect transistor with minimal contact to gate erosion
IBM0 citations62
US12356711B2Jul 8, 2025
Late gate extension
IBM0 citations62
US12249643B2Mar 11, 2025
Stacked planar field effect transistors with 2D material channels
IBM0 citations62
US11908923B2Feb 20, 2024
Low-resistance top contact on VTFET
IBM0 citations62
US11742350B2Aug 29, 2023
Metal gate N/P boundary control by active gate cut and recess
IBM0 citations62
US11646373B2May 9, 2023
Vertical field effect transistor with bottom spacer
IBM0 citations62
US11217692B2Jan 4, 2022
Vertical field effect transistor with bottom spacer
IBM0 citations62
US11205723B2Dec 21, 2021
Selective source/drain recess for improved performance, isolation, and scaling
IBM1 citations62
US10833173B2Nov 10, 2020
Low-resistance top contact on VTFET
IBM1 citations62
US12243770B2Mar 4, 2025
Hard mask removal without damaging top epitaxial layer
IBM0 citations61
US10943992B2Mar 9, 2021
Transistor having straight bottom spacers
IBM0 citations60
US11263059B2Mar 1, 2022
Load leveler
IBM1 citations58
US11005646B2May 11, 2021
Blockchain stochastic timer transaction synchronization
IBM0 citations58
US12136656B2Nov 5, 2024
Semiconductor structure having two-dimensional channel
IBM0 citations52
US11916013B2Feb 27, 2024
Via interconnects including super vias
IBM0 citations52
US11351811B2Jun 7, 2022
Optically-passive magnetic signature and identification feature with electromagnetic tamper detection
IBM0 citations52
US10833172B2Nov 10, 2020
Gate stack reliability in vertical transport field effect transistors
IBM0 citations52
US10741452B2Aug 11, 2020
Controlling fin hardmask cut profile using a sacrificial epitaxial structure
IBM0 citations52
US10546813B2Jan 28, 2020
BEOL vertical fuse formed over air gap
IBM0 citations52
US10453793B2Oct 22, 2019
BEOL vertical fuse formed over air gap
IBM0 citations52
US10083908B2Sep 25, 2018
BEOL vertical fuse formed over air gap
IBM0 citations52
US9997454B2Jun 12, 2018
BEOL vertical fuse formed over air gap
IBM0 citations52
Showing the top 50 of 52 patents by PatentIndex Score.