Inventor

WANG MIAOMIAO

US50 patents

⚠️ This page may combine multiple inventors who share the name “WANG MIAOMIAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG MIAOMIAO

IBM

High-k and p-type work function metal first fabrication process having improved annealing process flows

External resistance reduction with embedded bottom source/drain for vertical transport FET

Electrostatic discharge protection using vertical fin CMOS technology

Parasitic capacitance reducing contact structure in a finFET

Metal FinFET anti-fuse

Planar devices with consistent base dielectric

Dual FIN integration for electron and hole mobility enhancement

Dual fin integration for electron and hole mobility enhancement

Protection diode to prevent charge damage during MOL

Separate gate complementary field-effect transistor

Stacked complementary field effect transistors

Static random access memory device with stacked FETs

Resistance tunable fuse structure formed by embedded thin metal layers

Nanosheet transistor with ferroelectric region

Stacked complementary field effect transistors

Layout design for threshold voltage tuning

Resistance tunable fuse structure formed by embedded thin metal layers

Resistance tunable fuse structure formed by embedded thin metal layers

External resistance reduction with embedded bottom source/drain for vertical transport FET

In-situ chip design for pulse IV self-heating evaluation

Semiconductor device with a protective diode connected to a fuse

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

Semiconductor structure having stacked power rails

Electrostatic discharge diode having dielectric isolation layer

Self-aligned gate contact for VTFETs

Gate stack reliability in vertical transport field effect transistors

High density antifuse co-integrated with vertical FET

High density antifuse co-integrated with vertical FET

Parasitic capacitance reducing contact structure in a finFET

Parasitic capacitance reducing contact structure in a finFET

Parasitic capacitance reducing contact structure in a finFET

Metal FinFET anti-fuse

High-k and p-type work function metal first fabrication process having improved annealing process flows

Dual fin integration for electron and hole mobility enhancement

Dual fin integration for electron and hole mobility enhancement

Decoupling BTI and HCI mechanism in ring oscillator

FANUC CORP

Optical encoder for preventing crosstalk

Rotary motion detecting device

Optical encoder including stationary slit part having elastic structure

Encoder

SHANGHAI AVIC OPTOELECTRONICS

TFT array substrate, display panel and display device

Array substrate, display panel and display device

Array substrate, display panel and display device

INVESTIGEN INC

Methods and compositions for rapid light-activated isolation and detection of analytes

Methods and compositions for detecting polynucleotides

GOERTEK INC

Intelligent head-mounted apparatus

Intelligent head-mounted apparatus

CHINALCO RESEARCH INSTITUTE OF SCIENCE AND TECH CO LTD

Fine-grain tin-phosphor bronze alloy strip and a preparation method thereof

Modified tin-phosphor bronze alloy and a preparation method thereof

BEIJING INST CONTROL ENG

Apparatus and method for measuring micro-vibration influence of spatial orientation measuring instrument