Inventor

JAGANNATHAN HEMANTH

US229 patents

⚠️ This page may combine multiple inventors who share the name “JAGANNATHAN HEMANTH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAGANNATHAN HEMANTH

IBM

Forming wrap-around silicide contact on finFET

Planar and non-planar CMOS devices with multiple tuned threshold voltages

Formation of self-aligned bottom spacer for vertical transistors

Vertical transport field-effect transistor including dual layer top spacer

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

Bottom contact resistance reduction on VFET

VTFET devices utilizing low temperature selective epitaxy

Fabrication of silicon-germanium fin structure having silicon-rich outer surface

Isolation of bulk FET devices with embedded stressors

Stacked planar capacitors with scaled EOT

Dual metal interconnect structure

Controlling threshold voltage in nanosheet transistors

Silicon-germanium semiconductor devices and method of making

Fin cut enabling single diffusion breaks

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Forming wrap-around silicide contact on finFET

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme

Simplified gate stack process to improve dual channel CMOS performance

Self-aligned double patterning formed fincut

High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process

Vertical transport field-effect transistor including air-gap top spacer

Oxide isolated fin-type field-effect transistors

Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device

Wrap-around-contact structure for top source/drain in vertical FETs

Replacement metal gate processes for vertical transport field-effect transistor

VFET metal gate patterning for vertical transport field effect transistor

Dual channel CMOS having common gate stacks

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

Metal cap protection layer for gate and contact metallization

Structure and method for replacement gate integration with self-aligned contacts

Solid state diffusion doping for bulk finFET devices

Structure for integration of an III-V compound semiconductor on SOI

III-V semiconductor CMOS FinFET device

III-V fin on insulator

Replacement metal gate FinFET

Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate

Divot-free planarization dielectric layer for replacement gate

Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins

Replacement metal gate FinFET

Replacement metal gate FinFET

Structure and method for stress latching in non-planar semiconductor devices

Robust replacement gate integration

JAGANNATHAN HEMANTH

Replacement gate electrode with multi-thickness conductive metallic nitride layers

Stratified gate dielectric stack for gate dielectric leakage reduction

Replacement gate electrode with multi-thickness conductive metallic nitride layers

High performance non-planar semiconductor devices with metal filled inter-fin gaps

UNIV LELAND STANFORD JUNIOR

Microfluidic channels with integrated ultrasonic transducers for temperature measurement and method

CHENG KANGGUO

Method for integrating multiple threshold voltage devices for CMOS