Inventor
ANANTHA NARASIPUR G
US22 patents
Patents
22 patentsUS4252582AFeb 24, 1981
Self aligned method for making bipolar transistor having minimum base to emitter contact spacing
IBM58 citations96
US4691435ASep 8, 1987
Method for making Schottky diode having limited area self-aligned guard ring
IBM35 citations92
US4583106AApr 15, 1986
Fabrication methods for high performance lateral bipolar transistors
IBM39 citations92
US4546536AOct 15, 1985
Fabrication methods for high performance lateral bipolar transistors
IBM42 citations92
US4492008AJan 8, 1985
Methods for making high performance lateral bipolar transistors
IBM31 citations92
US4427989AJan 24, 1984
High density memory cell
IBM29 citations92
US4389281AJun 21, 1983
Method of planarizing silicon dioxide in semiconductor devices
IBM32 citations92
US4269631AMay 26, 1981
Selective epitaxy method using laser annealing for making filamentary transistors
IBM30 citations92
US4236294ADec 2, 1980
High performance bipolar device and method for making same
IBM31 citations92
US4228450AOct 14, 1980
Buried high sheet resistance structure for high density integrated circuits with reach through contacts
IBM30 citations92
US4160991AJul 10, 1979
High performance bipolar device and method for making same
IBM45 citations92
US4228369AOct 14, 1980
Integrated circuit interconnection structure having precision terminating resistors
IBM32 citations91
US4264382AApr 28, 1981
Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions
IBM51 citations89
US4139910AFeb 13, 1979
Charge coupled device memory with method of doubled storage capacity and independent of process parameters and temperature
IBM42 citations88
US4214315AJul 22, 1980
Method for fabricating vertical NPN and PNP structures and the resulting product
IBM25 citations82
US4159915AJul 3, 1979
Method for fabrication vertical NPN and PNP structures utilizing ion-implantation
IBM28 citations82
US4196440AApr 1, 1980
Lateral PNP or NPN with a high gain
IBM23 citations81
US4510676AApr 16, 1985
Method of fabricating a lateral PNP transistor
IBM26 citations80
US4796069AJan 3, 1989
Schottky diode having limited area self-aligned guard ring and method for making same
IBM10 citations73
US4389294AJun 21, 1983
Method for avoiding residue on a vertical walled mesa
IBM17 citations73
US4252581AFeb 24, 1981
Selective epitaxy method for making filamentary pedestal transistor
IBM19 citations73
US4316319AFeb 23, 1982
Method for making a high sheet resistance structure for high density integrated circuits
IBM5 citations62