Inventor

RISEMAN JACOB

US34 patents

Patents

34 patents

US4419809ADec 13, 1983

Fabrication process of sub-micrometer channel length MOSFETs

IBM332 citations99

US4234362ANov 18, 1980

Method for forming an insulator between layers of conductive material

IBM288 citations99

US4671851AJun 9, 1987

Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique

IBM189 citations98

US4648937AMar 10, 1987

Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer

IBM348 citations98

US4944836AJul 31, 1990

Chem-mech polishing method for producing coplanar metal/insulator films on a substrate

IBM539 citations97

US4521952AJun 11, 1985

Method of making integrated circuits using metal silicide contacts

IBM81 citations96

US4419810ADec 13, 1983

Self-aligned field effect transistor process

IBM89 citations96

US4356211AOct 26, 1982

Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon

IBM102 citations96

US4169000ASep 25, 1979

Method of forming an integrated circuit structure with fully-enclosed air isolation

IBM79 citations96

US4462040AJul 24, 1984

Single electrode U-MOSFET random access memory

IBM60 citations95

US4252579AFeb 24, 1981

Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition

IBM72 citations95

US4209350AJun 24, 1980

Method for forming diffusions having narrow dimensions utilizing reactive ion etching

IBM65 citations95

US4209349AJun 24, 1980

Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching

IBM95 citations95

US4090254AMay 16, 1978

Charge injector transistor memory

IBM57 citations94

US4641170AFeb 3, 1987

Self-aligned lateral bipolar transistors

IBM32 citations93

US4032058AJun 28, 1977

Beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads

IBM44 citations93

US4729006AMar 1, 1988

Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads

IBM31 citations82

US4544576AOct 1, 1985

Deep dielectric isolation by fused glass

IBM24 citations81

US3943542AMar 9, 1976

High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same

IBM30 citations81

US4464212AAug 7, 1984

Method for making high sheet resistivity resistors

IBM11 citations74

US4106050AAug 8, 1978

Integrated circuit structure with fully enclosed air isolation

IBM12 citations74

US3972754AAug 3, 1976

Method for forming dielectric isolation in integrated circuits

IBM12 citations74

US4054989AOct 25, 1977

High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same

IBM8 citations73

US4017883AApr 12, 1977

Single-electrode charge-coupled random access memory cell with impurity implanted gate region

IBM10 citations73

US4070687AJan 24, 1978

Composite channel field effect transistor and method of fabrication

IBM17 citations71

US4712125ADec 8, 1987

Structure for contacting a narrow width PN junction region

IBM18 citations70

RISEMAN JACOB

Patents

Fabrication process of sub-micrometer channel length MOSFETs

Method for forming an insulator between layers of conductive material

Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique

Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer

Chem-mech polishing method for producing coplanar metal/insulator films on a substrate

Method of making integrated circuits using metal silicide contacts

Self-aligned field effect transistor process

Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon

Method of forming an integrated circuit structure with fully-enclosed air isolation

Single electrode U-MOSFET random access memory

Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition

Method for forming diffusions having narrow dimensions utilizing reactive ion etching

Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching

Charge injector transistor memory

Self-aligned lateral bipolar transistors

Beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads

Sidewall spacers for CMOS circuit stress relief/isolation and method for making

Process for forming planar chip-level wiring

Fabrication methods for high performance lateral bipolar transistors

Fabrication methods for high performance lateral bipolar transistors

Method for forming recessed isolated regions

Method for forming a planarized integrated circuit

Method for contacting a narrow width PN junction region

Method for making self-aligned lateral bipolar transistors

Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads

Deep dielectric isolation by fused glass

High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same

Method for making high sheet resistivity resistors

Integrated circuit structure with fully enclosed air isolation

Method for forming dielectric isolation in integrated circuits

High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same

Single-electrode charge-coupled random access memory cell with impurity implanted gate region

Composite channel field effect transistor and method of fabrication

Structure for contacting a narrow width PN junction region