Inventor

NATZLE WESLEY C

US41 patents

⚠️ This page may combine multiple inventors who share the name “NATZLE WESLEY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NATZLE WESLEY C

IBM

Device and method for accurate etching and removal of thin film

Metal oxide field effect transistor with a sharp halo

Damascene double-gate MOSFET with vertical channel regions

Structure and method for producing low leakage isolation devices

Trench sidewall patterned by vapor phase etching

Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer

Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures

Vapor phase etching of oxide masked by resist or masking material

Method of patterning sidewalls of a trench in integrated circuit manufacturing

Oxide layer patterned by vapor phase etching

Oxide strip that improves planarity

Sealed chamber with heating lamps provided within transparent tubes

Method of making sub-lithographic features

MOSFET device with in-situ doped, raised source and drain structures

Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling

Method for reducing line edge roughness of oxide material using chemical oxide removal

Damascene double-gate MOSFET with vertical channel regions

Supersonic molecular beam etching of surfaces

Supersonic molecular beam etching of surfaces

Vapor phase etch trim structure with top etch blocking layer

Thin film resistor and method for producing same

Folded trench and rie/deposition process for high-value capacitors

Nitrogen based plasma process for metal gate MOS device

Field effect device with reduced thickness gate

Structure and method to fabricate ultra-thin Si channel devices

Freestanding multiplayer IC wiring structure

Etch selectivity enhancement for tunable etch resistant anti-reflective layer

Folded trench and RIE/deposition process for high-value capacitors

Subgroundrule space for improved metal high-k device

Metal oxide field effect transistor with a sharp halo and a method of forming the transistor

Clustered surface preparation for silicide and metal contacts

Structure and method to control oxidation in high-k gate structures

Feature dimension deviation correction system, method and program product

MO RENEE T

High-k/metal gate transistor with L-shaped gate encapsulation layer

High-k/metal gate transistor with L-shaped gate encapsulation layer

BU HUIMING

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof

TOKYO ELECTRON LTD

Feature dimension deviation correction system, method and program product

CHAKRAVARTI ASHIMA B

Selective deposition of germanium spacers on nitride

AMOS RICKY S

Field effect device with reduced thickness gate

DALTON TIMOTHY J

Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist