Inventor
JAIN PALKESH
IN22 patents
⚠️ This page may combine multiple inventors who share the name “JAIN PALKESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
12 patentsUS9628089B1Apr 18, 2017
Supply voltage tracking clock generator in adaptive clock distribution systems
QUALCOMM INC23 citations92
US9897651B2Feb 20, 2018
Ultra-fast autonomous clock monitoring circuit for safe and secure automotive applications
QUALCOMM INC8 citations82
US11424621B2Aug 23, 2022
Configurable redundant systems for safety critical applications
QUALCOMM INC2 citations72
US10389379B2Aug 20, 2019
Error correcting code testing
QUALCOMM INC2 citations71
US10089194B2Oct 2, 2018
System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems
QUALCOMM INC5 citations71
US10901020B2Jan 26, 2021
Digital duty-cycle monitoring of a periodic signal
QUALCOMM INC3 citations67
US10591965B2Mar 17, 2020
System and method for context-aware thermal management and workload scheduling in a portable computing device
QUALCOMM INC1 citations61
US11416049B2Aug 16, 2022
In-field monitoring of on-chip thermal, power distribution network, and power grid reliability
QUALCOMM INC0 citations51
US9915968B2Mar 13, 2018
Systems and methods for adaptive clock design
QUALCOMM INC1 citations51
US10141297B1Nov 27, 2018
Integrated device comprising device level cells with variable sizes for heat dissipation around hotspots
QUALCOMM INC0 citations48
US10103714B2Oct 16, 2018
Adjust voltage for thermal mitigation
QUALCOMM INC0 citations48
US10042405B2Aug 7, 2018
Adjusting source voltage based on stored information
QUALCOMM INC0 citations41
JAIN PALKESH
5 patentsUS8219953B2Jul 10, 2012
Budgeting electromigration-related reliability among metal paths in the design of a circuit
JAIN PALKESH9 citations79
US8786307B2Jul 22, 2014
Bias temperature instability-resistant circuits
JAIN PALKESH6 citations71
US8255850B2Aug 28, 2012
Fabricating IC with NBTI path delay within timing constraints
JAIN PALKESH5 citations58
US8677303B2Mar 18, 2014
Electromigration compensation system
JAIN PALKESH0 citations51
US8296701B2Oct 23, 2012
Method for designing a semiconductor device based on leakage current estimation
JAIN PALKESH1 citations42
TEXAS INSTRUMENTS INC
4 patentsUS7689377B2Mar 30, 2010
Technique for aging induced performance drift compensation in an integrated circuit
TEXAS INSTRUMENTS INC11 citations83
US7752582B2Jul 6, 2010
Method and apparatus for determining electro-migration in integrated circuit designs
TEXAS INSTRUMENTS INC9 citations80
US8013635B2Sep 6, 2011
Multi-mode circuit and a method for preventing degradation in the multi-mode circuit
TEXAS INSTRUMENTS INC6 citations60
US7791926B2Sep 7, 2010
SEU hardening circuit and method
TEXAS INSTRUMENTS INC0 citations51