Inventor

MASLEID ROBERT PAUL

US65 patents

⚠️ This page may combine multiple inventors who share the name “MASLEID ROBERT PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MASLEID ROBERT PAUL

IBM

Gain enhanced split drive buffer

Low voltage CMOS differential amplifier

Clock regulator with precision midcycle edge timing

Clock distribution network for reducing clock skew

Data processing system having memory sub-array redundancy and method therefor

Method and apparatus for phase rotation in a phase locked loop

Method and apparatus for coupled phase locked loops

Precision time interval division with digital phase delay lines

Power management system for integrated circuits

High gain local clock buffer for a mesh clock distribution utilizing a gain enhanced split driver clock buffer

Method and system for building a multiprocessor data processing system

Creating inversions in ripple domino logic

High Speed SRAM with or-gate sense

Fast read domino SRAM

Decoupled reset dynamic logic circuit

System and method for robust clocking schemes for logic circuits

Cache sub-array method and apparatus for use in microprocessor integrated circuits

Circuit having anti-charge share characteristics and method therefore

Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator

Method and apparatus for process independent clock signal distribution

TRANSMETA CORP

Circuits and methods for detecting and assisting wire transitions

Leakage efficient anti-glitch filter

Configurable delay chain with stacked inverter delay elements

Elastic pipeline latch with a safe mode

Systems and methods for adjusting threshold voltage

Repeater circuit with high performance repeater mode and normal repeater mode

Circuits and methods for detecting and assisting wire transitions

Low RC structures for routing body-bias voltage

Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability

Repeater circuit having different operating and reset voltage ranges, and methods thereof

Leakage efficient anti-glitch filter with variable delay stages

Wire mesh patterns for semiconductor devices

Method and system for tiling a bias design to facilitate efficient design rule checking

Advanced repeater utilizing signal distribution delay

MASLEID ROBERT PAUL

Systems and methods for adjusting threshold voltage

Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability

Systems and methods for adjusting threshold voltage

Power efficient multiplexer

Systems and methods for adjusting threshold voltage

Power efficient multiplexer

Inverting zipper repeater circuit

Column select multiplexer circuit for a domino random access memory array

Configurable delay chain with switching control for tail delay elements

Systems and methods for voltage distribution via multiple epitaxial layers

Configurable delay chain with stacked inverter delay elements

Circuits and methods for detecting and assisting wire transitions

KONIARIS KLEANTHES G

Systems and methods for integrated circuits comprising multiple body biasing domains

Systems and methods for integrated circuits comprising multiple body biasing domains

INTELLECTUAL VENTURE FUNDING LLC

Power efficient multiplexer

PITKETHLY SCOTT

Advanced repeater utilizing signal distribution delay