Inventor

YAO HSIN-CHIEH

TW52 patents

⚠️ This page may combine multiple inventors who share the name “YAO HSIN-CHIEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAO HSIN-CHIEH

TAIWAN SEMICONDUCTOR MFG CO LTD

Methods of forming interconnect structures in semiconductor fabrication

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Dual etch-stop layer structure

Selective deposition of a protective layer to reduce interconnect structure critical dimensions

Self-aligned interconnect structure

Selective deposition of a protective layer to reduce interconnect structure critical dimensions

Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability

System and method for dark field inspection

Tapered sidewall conductive lines and formation thereof

Semiconductor devices and methods of manufacture thereof

Semiconductor device structure and methods of forming the same

Extreme ultraviolet (EUV) mask and method of fabricating the EUV mask

Semiconductor structure

Semiconductor device structure and methods of forming the same

Interconnection structure and methods of forming the same

Self-assembled dielectric on metal rie lines to increase reliability

Self-aligned interconnect structure

Dielectric on wire structure to increase processing window for overlying via

Structure and formation method of semiconductor device with carbon-containing conductive structure

Integrated chip with an etch-stop layer forming a cavity

Double patterning approach by direct metal etch

Integrated chip with inter-wire cavities

Interconnection structure and methods of forming the same

Semiconductor device structure having air gap and method for forming the same

Barrier structure on interconnect wire to increase processing window for overlying via

Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability

Dual etch-stop layer structure

Integrated chip with inter-wire cavities

Self-assembled dielectric on metal RIE lines to increase reliability

Interconnection structure and methods of forming the same

Semiconductor structure and method for forming the same

Dielectric on wire structure to increase processing window for overlying via

Double patterning approach by direct metal etch

Self-aligned interconnect structure

Method of forming an integrated chip having a cavity between metal features

Interconnect conductive structure comprising two conductive materials

Semiconductor devices and methods of forming the same

Method for interconnect scheme

Method of semiconductor integrated circuit fabrication

TAIWAN SEMICONDUCTOR MFG

System and method for dark field inspection

Semiconductor devices and methods of manufacture thereof

System and method for chemical-mechanical planarization of a metal layer

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Interconnection wires of semiconductor devices

Method of semiconducotr integrated circuit fabrication

Interconnection wires of semiconductor devices

Integrated circuit formed using spacer-like copper deposition

Semiconductor devices and methods of manufacture thereof

YAO HSIN-CHIEH

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