Inventor

SPOONER TERRY A

US81 patents

⚠️ This page may combine multiple inventors who share the name “SPOONER TERRY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SPOONER TERRY A

IBM

Structure and method for metal integration

Surface nitridation in metal interconnects

Self aligned via in integrated circuit

Copper conductor

Semiconductor via structure with lower electrical resistance

Low resistance metal contacts to interconnects

Self aligned via and pillar cut for at least a self aligned double pitch

Surface treatment of inter-layer dielectric

Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer

Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair

Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices

Adhesion enhancement for metal/dielectric interface

Via formation using sidewall image transfer process to define lateral dimension

Via formation using sidewall image transfer process to define lateral dimension

Self aligned via in integrated circuit

Nitridization for semiconductor structures

Integrated circuit fabrication process using gas cluster ion beam etching

Adhesion enhancement for metal/dielectric interface

Back end of the line structures with liner and noble metal layer

Contacts having a geometry to reduce resistance

Low resistance contact for transistors

Semiconductor via structure with lower electrical resistance

Interconnect structure

Low resistance metal contacts to interconnects

Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement

Mechanically robust metal/low-κ interconnects

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer

Contacts having a geometry to reduce resistance

Interconnect structures including self aligned vias

Interconnect structures including self aligned vias

Semiconductor via structure with lower electrical resistance

Self aligned via and pillar cut for at least a self aligned double pitch

Self aligned via and pillar cut for at least a self aligned double pitch

Low resistance contact for transistors

Surface modified dielectric refill structure

GLOBALFOUNDRIES INC

Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks

Metal on metal multiple patterning

Multiple patterning with lithographically-defined cuts

Interconnect formation with chamferless via, and related interconnect

ARNOLD JOHN C

Methods to mitigate plasma damage in organosilicate dielectrics

Methods to mitigate plasma damage in organosilicate dielectrics

Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer

EDELSTEIN DANIEL C

Microelectronic structure including air gap

Microelectronic structure including air gap

CHEN SHYNG-TSONG

Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same

Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same

YANG CHIH-CHAO

Interconnect structure containing non-damaged dielectric and a via gouging feature

INFINEON TECHNOLOGIES AG

Back end interconnect with a shaped interface

INT BUSINESS MACHINES INT

Multiple pre-clean processes for interconnect fabrication

OU YA

Interconnect structure and method of making same