Inventor

PAYER STEFAN

DE29 patents

⚠️ This page may combine multiple inventors who share the name “PAYER STEFAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAYER STEFAN

IBM

Rapid character substring searching

Non-overlapping substring detection within a data element string

Dynamic algorithm selection

Rounding hexadecimal floating point numbers using binary incrementors

Vector string search instruction

Fault-tolerant clock gating

Vector string search instruction

Method and apparatus for wiring multiple technology evaluation circuits

Parallelized rounding for decimal floating point to binary coded decimal conversion

Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

Plausability-driven fault detection in result logic and condition codes for fast exact substring match

Rapid partial substring matching

Integrated circuit schematics having imbedded scaling information for generating a design instance

Method to limit the time a semiconductor device operates above a maximum operating voltage

Parallel rounding for conversion from binary floating point to binary coded decimal

Floating-point conversion with denormalization

Verifying the correctness of a leading zero counter

Hexadecimal floating point multiply and add instruction

Instruction scheduling during execution in a processor

Plausibility-driven fault detection in string termination logic for fast exact substring match

Integrated circuit control latch protection

Automated stressing and testing of semiconductor memory cells

Automated stressing and testing of semiconductor memory cells

Stressing and testing semiconductor memory cells

Clock-gating for multicycle instructions

Clock-gating for multicycle instructions

Automatic built-in self test for memory arrays

Rapid substring detection within a data element string

DENGLER OSAMA

Enhanced power savings for memory arrays