Inventor

CONTI ANNA MARIA

IT42 patents

⚠️ This page may combine multiple inventors who share the name “CONTI ANNA MARIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CONTI ANNA MARIA

MICRON TECHNOLOGY INC

Tapered cell profile and fabrication

Enhancing nucleation in phase-change memory cells

Flash memory having multi-level architecture

Flash memory having multi-level architecture

Memory cells for storing operational data

Memory cells with asymmetrical electrode interfaces

Three-dimensional memory array

Memory cells with asymmetrical electrode interfaces

Self-aligned memory decks in cross-point memory arrays

Array of gated devices and methods of forming an array of gated devices

Enhancing nucleation in phase-change memory cells

Enhancing nucleation in phase-change memory cells

Array of gated devices and methods of forming an array of gated devices

Self-aligned memory decks in cross-point memory arrays

Self-aligned memory decks in cross-point memory arrays

Microelectronic devices, memory devices, and electronic systems, and methods of forming the same

Microelectronic devices including staircase structures, and related memory devices, electronic systems, and methods

Memory cells with asymmetrical electrode interfaces

Access line formation for a memory array

Implementations to store fuse data in memory devices

Memory cells for storing operational data

Three-dimensional memory array

Tapered cell profile and fabrication

Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells

Access line formation for a memory array

Implementations to store fuse data in memory devices

Three-dimensional memory array

Array of gated devices and methods of forming an array of gated devices

Method used in forming memory circuitry having non-SGD stair-step structures individually having the collective stairs in one of its flights to have at least two different horizontal depths

Tapered cell profile and fabrication

Memory cells with asymmetrical electrode interfaces

Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells

Techniques for forming a device with scribe asymmetry

Enhancing nucleation in phase-change memory cells

Techniques for manufacturing a double electrode memory array

Array of gated devices and methods of forming an array of gated devices

INTEL CORP

Memory structures having improved write endurance

Via resistance reduction

Memory structures having reduced via resistance

Memory structures having improved write endurance

Memory device with double protective liner

GROSSI ALESSANDRO

Multi-layer flash memory