Inventor
NG AARON
US24 patents
Patents
24 patentsUS10515135B1Dec 24, 2019
Data format suitable for fast massively parallel general matrix multiplication in a programmable IC
XILINX INC25 citations94
US10460416B1Oct 29, 2019
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
XILINX INC19 citations94
US10354733B1Jul 16, 2019
Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC
XILINX INC40 citations94
US11204747B1Dec 21, 2021
Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions
XILINX INC19 citations93
US10192016B2Jan 29, 2019
Neural network based physical synthesis for circuit designs
XILINX INC49 citations90
US11222256B2Jan 11, 2022
Neural network processing system having multiple processors and a neural network accelerator
XILINX INC8 citations85
US10943039B1Mar 9, 2021
Software-driven design optimization for fixed-point multiply-accumulate circuitry
XILINX INC11 citations85
US10678509B1Jun 9, 2020
Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators
XILINX INC11 citations85
US11036827B1Jun 15, 2021
Software-defined buffer/transposer for general matrix multiplication in a programmable IC
XILINX INC7 citations84
US9646126B1May 9, 2017
Post-routing structural netlist optimization for circuit designs
XILINX INC7 citations83
US10936311B1Mar 2, 2021
Sparse matrix processing circuitry
XILINX INC8 citations81
US11568218B2Jan 31, 2023
Neural network processing system having host controlled kernel acclerators
XILINX INC5 citations74
US11429848B2Aug 30, 2022
Host-directed multi-layer neural network processing via per-layer work requests
XILINX INC4 citations73
US11386644B2Jul 12, 2022
Image preprocessing for generalized image processing
XILINX INC2 citations73
US10984500B1Apr 20, 2021
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
XILINX INC3 citations73
US11620490B2Apr 4, 2023
Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions
XILINX INC3 citations72
US10366201B1Jul 30, 2019
Timing closure of circuit designs for integrated circuits
XILINX INC5 citations72
US9965581B1May 8, 2018
Fanout optimization to facilitate timing improvement in circuit designs
XILINX INC6 citations72
US9836568B1Dec 5, 2017
Programmable integrated circuit design flow using timing-driven pipeline analysis
XILINX INC6 citations69
US7840919B1Nov 23, 2010
Resource mapping of functional areas on an integrated circuit
XILINX INC6 citations62
US12079158B2Sep 3, 2024
Reconfigurable neural engine with extensible instruction set architecture
XILINX INC0 citations58
US12412109B2Sep 9, 2025
Machine learning deployment platform
XILINX INC0 citations52
US11694066B2Jul 4, 2023
Machine learning runtime library for neural network acceleration
XILINX INC0 citations51
US12248786B2Mar 11, 2025
Instruction set architecture for data processing array control
XILINX INC0 citations43