Inventor

SCHMOOKLER MARTIN S

US16 patents

⚠️ This page may combine multiple inventors who share the name “SCHMOOKLER MARTIN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

12 patents

US4903228AFeb 20, 1990

Single cycle merge/logic unit

IBM99 citations94

US5957997ASep 28, 1999

Efficient floating point normalization mechanism

IBM43 citations92

US5129066AJul 7, 1992

Bit mask generator circuit using multiple logic units for generating a bit mask sequence

IBM23 citations92

US5930148AJul 27, 1999

Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques

IBM78 citations91

US5493520AFeb 20, 1996

Two state leading zero/one anticipator (LZA)

IBM42 citations91

US7730117B2Jun 1, 2010

System and method for a floating point unit with feedback prior to normalization and rounding

IBM13 citations84

US5764549AJun 9, 1998

WEINBERG JOSHUA M

4 patents

US8402078B2Mar 19, 2013

Method, system and computer program product for determining required precision in fixed-point divide operations

WEINBERG JOSHUA M8 citations81

US8713084B2Apr 29, 2014

Method, system and computer program product for verifying floating point divide operation results

WEINBERG JOSHUA M4 citations70

US8626816B2Jan 7, 2014

Method, system and computer program product for detecting errors in fixed point division operation results

WEINBERG JOSHUA M3 citations60

US8745118B2Jun 3, 2014

Verifying floating point square root operation results

WEINBERG JOSHUA M0 citations49

SCHMOOKLER MARTIN S

IBM

Single cycle merge/logic unit

Efficient floating point normalization mechanism

Bit mask generator circuit using multiple logic units for generating a bit mask sequence

Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques

Two state leading zero/one anticipator (LZA)

System and method for a floating point unit with feedback prior to normalization and rounding

Fast floating point result alignment apparatus

Adder circuits and magnitude comparator

Scannable latch for multiplexor control

Arithmetic logic circuit having a carry generator

Adder with improved carry lookahead structure

Logic array with programmable element output generation

WEINBERG JOSHUA M

Method, system and computer program product for determining required precision in fixed-point divide operations

Method, system and computer program product for verifying floating point divide operation results

Method, system and computer program product for detecting errors in fixed point division operation results

Verifying floating point square root operation results