Inventor

RAJSKI JANUSZ

US131 patents

⚠️ This page may combine multiple inventors who share the name “RAJSKI JANUSZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJSKI JANUSZ

RAJSKI JANUSZ

Test pattern compression for an integrated circuit test environment

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Multi-stage test response compactors

Low power decompression of test cubes

Method and apparatus for selectively compacting test responses

Compressing test responses using a compactor

Determining and analyzing integrated circuit yield and quality

Phase shifter with reduced linear dependency

Decompressors for low power decompression of test patterns

Phase shifter with reduced linear dependency

Test pattern compression for an integrated circuit test environment

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Continuous application and decompression of test patterns to a circuit-under-test

Phase shifter with reduced linear dependency

Method for synthesizing linear finite state machines

Method and apparatus for at-speed testing of digital circuits

Arithmetic built-in self-test of multiple scan-based integrated circuits

Selective per-cycle masking of scan chains for system level test

Compressing test responses using a compactor

Fault diagnosis of compressed test responses

Fault diagnosis of compressed test responses having one or more unknown states

Adaptive fault diagnosis of compressed test responses

(unassigned)

Phase shifter with reduced linear dependency

Method and apparatus for selectively compacting test responses

Arithmetic built-in self-test of multiple scan-based integrated circuits

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

Test pattern compression for an integrated circuit test environment

Method for synthesizing linear finite state machines

Test pattern compression for an integrated circuit test environment

Method for synthesizing linear finite state machines

Method for clustered test pattern generation

Method for synthesizing linear finite state machines

Method and apparatus for diagnosing memory using self-testing circuits

MENTOR GRAPHICS CORP

Parallel decompressor and related methods and apparatuses

Arithmetic built-in self test of multiple scan-based integrated circuits

On-chip comparison and response collection tools and techniques

Multi-phase test point insertion for built-in self test of integrated circuits

Data generation for streaming networks in circuits

Test pattern compression for an integrated circuit test environment

Continuous application and decompression of test patterns to a circuit-under-test

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

Fault dictionaries for integrated circuit yield and quality analysis methods and systems

Low power scan testing techniques and apparatus

Multi-phase test point insertion for built-in self test of integrated circuits

HUANG YU

Compactor independent direct diagnosis of test hardware

Compactor independent direct diagnosis of test hardware

CHENG WU-TUNG

Compactor independent fault diagnosis

MUKHERJEE NILANJAN

On-chip comparison and response collection tools and techniques