Inventor

HAMANAKA NAOKI

JP42 patents

⚠️ This page may combine multiple inventors who share the name “HAMANAKA NAOKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAMANAKA NAOKI

HITACHI LTD

Node controller for performing cache coherence control and memory-shared multiprocessor system

Virtual computer system with dynamic resource reallocation

Multiprocessor system with partial broadcast capability of a cache coherent processing request

Inter-processor communication method for transmitting data and processor dependent information predetermined for a receiving process of another processor

Fabric and method for sharing an I/O device among virtual machines formed in a computer system

Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks and exchangers

Virtual computer systems and computer virtualization programs

Method for storing records of a distributed database by plural processors to provide a host processor with sorted records belonging to one of a plurality of key sections

Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers

Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors

Method and apparatus for transferring vector data between parallel processing system with registers &amp; logic for inter-processor data communication independents of processing operations

Parallel computer with distributed shared memories and distributed task activating circuits

Multiprocessor system and cache coherency control method

Partial broadcast method in parallel computer and a parallel computer suitable therefor

Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism

Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism

Shared memory multiprocessor performing cache coherence control and node controller therefor

Multi-processor system and its network

Cache control system

Multiprocessor system and methods for transmitting memory access transactions for the same

Multiprocessor system

Semiconductor integrated circuit system having function of automatically adjusting output resistance value

Multi-processor system and its network

Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same

Arbitration circuit capable of changing the priority and arrival time of nonselected requests

Parallel computer with asynchronous communication facility

Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems

Virtual computer systems and computer virtualization programs

Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer

Shared memory multiprocessor performing cache coherence control and node controller therefor

Multiprocessor system

Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs

System for converting job/process identifiers into processor/process identifiers in transferring data between processes in a multiprocessor system

Computer for synchronized read and write of vector data

Cache coherent control system for network nodes allows cpu or i/o device to access target block without cache coherence control, if associated node has access right in an access right memory to target block

Switching system for transferring broadcast packet held in broadcast buffer received from input port to output ports according to the state of each output port

Data transfer network suitable for use in a parallel computer

Processor with a processor-accessible cache for data received from outside of the processor

Shared memory multiprocessor system

Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof

HAYASHI TAKEHISA

Data transfer network suitable for use in a parallel computer

KAWAMOTO SHINICHI

Virtual computer systems and computer virtualization programs

Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations