Inventor

PUZZILLI GIUSEPPINA

US37 patents

⚠️ This page may combine multiple inventors who share the name “PUZZILLI GIUSEPPINA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PUZZILLI GIUSEPPINA

MICRON TECHNOLOGY INC

In-field block retiring

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Threshold voltage distribution adjustment for buffer

Adjusting a preprogram voltage based on use of a memory device

Adjusting a preprogram voltage based on use of a memory device

Setting an initial erase voltage using feedback from previous operations

Erase operations and apparatus for a memory device

Mitigating slow read disturb in a memory sub-system

Mitigating slow read disturb in a memory sub-system

Implementing fault tolerant page stripes on low density memory systems

Latent read disturb mitigation in memory devices

Read calibration based on ranges of program/erase cycles

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Read voltage calibration for copyback operation

Read window based on program/erase cycles

Threshold voltage distribution adjustment for buffer

Trims corresponding to logical unit quantity

Partitioned memory having error detection capability

Implementing fault tolerant page stripes on low density memory systems

Trims corresponding to program/erase cycles

Read calibration based on ranges of program/erase cycles

Read voltage calibration for copyback operation

Separate trims for buffer and snapshot

Read window based on program/erase cycles

Temperature-dependent operations in a memory device

Threshold voltage based on program/erase cycles

Storing highly read data at low impact read disturb pages of a memory device

Data management during a copyback operation

Determining a read voltage based on a change in a read window

Methods of programming memory devices

INTEL CORP

Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND

GODA AKIRA

Data line management in a memory device

PUZZILLI GIUSEPPINA

Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source select gate

PARAT KRISHNA K

In-field block retiring

LODESTAR LICENSING GROUP LLC

Partitioned memory having error detection capability