Inventor

RIGHETTI NICCOLO′

US47 patents

⚠️ This page may combine multiple inventors who share the name “RIGHETTI NICCOLO′”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RIGHETTI NICCOLO′

MICRON TECHNOLOGY INC

Methods of forming memory arrays

Partial block handling in a non-volatile memory device

Adjustment of code rate as function of memory endurance state metric

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Threshold voltage distribution adjustment for buffer

Modified read counter incrementing scheme in a memory sub-system

Adjusting a preprogram voltage based on use of a memory device

Adjusting a preprogram voltage based on use of a memory device

Setting an initial erase voltage using feedback from previous operations

Dynamic block categorization to improve reliability and performance in memory sub-system

Adjustment of code rate as function of memory endurance state metric

Memory block characteristic determination

Partial block handling in a non-volatile memory device

Memory block characteristic determination

Latent read disturb mitigation in memory devices

Read calibration based on ranges of program/erase cycles

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Read voltage calibration for copyback operation

Read window based on program/erase cycles

Threshold voltage distribution adjustment for buffer

Trims corresponding to logical unit quantity

Partitioned memory having error detection capability

Trims corresponding to program/erase cycles

Read calibration based on ranges of program/erase cycles

Read voltage calibration for copyback operation

Separate trims for buffer and snapshot

Read window based on program/erase cycles

Modified read counter incrementing scheme in a memory sub-system

Temperature-dependent operations in a memory device

Dynamic block categorization to improve reliability and performance in memory sub-system

Adaptive read disturb scan

Read counter adjustment for delaying read disturb scans

Self-optimizing corrective read offsets with lateral charge migration proxies

Selectively programming retired wordlines of a memory device

Programming selective word lines during an erase operation in a memory device

Threshold voltage based on program/erase cycles

Data management during a copyback operation

Determining a read voltage based on a change in a read window

Data block transfer with extended read buffering

Media management scanning with unified criteria to alleviate fast and latent read disturb

System driven pass-through voltage adjustment to improve read disturb in memory devices

Read disturb tracking among multiple erase blocks coupled to a same string

Methods of forming memory arrays

INTEL CORP

Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND

LODESTAR LICENSING GROUP LLC

Partitioned memory having error detection capability