Inventor

SENINGEN MICHAEL R

US54 patents

⚠️ This page may combine multiple inventors who share the name “SENINGEN MICHAEL R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SENINGEN MICHAEL R

APPLE INC

Low power clock gating circuit

Memory with redundant sense amplifier

Level shifting circuit with data resolution and grounded input nodes

Reduced power set-reset latch based flip-flop

Power detection circuit

Memory with redundant sense amplifier

Data pattern based cache management

Data pattern based cache management

Data pattern based cache management

Level shifter with isolation on both input and output domains with enable from both domains

System control using sparse data

System control using sparse data

System control using sparse data

Output signal control during retention mode operation

Weak bit detection using on-die voltage modulation

Scan chain analysis using predefined capture signature

Flop circuit with integrated clock gating circuit

Transistor work function adjustment by laser stimulation

Transistor work function adjustment by laser stimulation

Memory with bit line current injection

System control using sparse data

Memory bit cell for in-memory computation

On-die system for monitoring and predicting performance

INTRINSITY INC

Method and apparatus for routing 1 of 4 signals

Method and apparatus for routing 1 of N signals

Method and apparatus for a RAM circuit having N-Nary output interface

Method and apparatus for a logic circuit with constant power consumption

Static storage element for dynamic logic

Dynamic logic scan gate method and apparatus

Method and apparatus for a 1 of N signal

Dynamic logic scan gate method and apparatus

Method and apparatus for an N-NARY logic circuit

Method and apparatus for 1 of 4 register file design

Method and apparatus for scan of synchronized dynamic logic using embedded scan gates

Method and apparatus for a N-nary logic circuit using capacitance isolation

Method and apparatus for a N-NARY logic circuit using capacitance isolation

SENINGEN MICHAEL R

Memory with variable strength sense amplifier

Goal-driven search of a stochastic process using reduced sets of simulation points

Memory with bit line capacitive loading

Memory with redundant sense amplifier

Pulse dynamic logic gates with LSSD scan functionality

Memory with bit line current injection

Pulse dynamic logic gates with mux-D scan functionality

Latch array utilizing through device connectivity

EVSX INC

Method and apparatus for a N-nary logic circuit using 1 of N signals

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Method and apparatus for a RAM circuit having N-nary output interface

Method and apparatus for an address triggered RAM circuit

Method and apparatus for multi-bit register cell

Method and apparatus for a RAM circuit having N-nary word line generation