Inventor

IADANZA JOSEPH A

US62 patents

⚠️ This page may combine multiple inventors who share the name “IADANZA JOSEPH A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IADANZA JOSEPH A

IBM

Cross-coupled bitline segments for generalized data propagation

Method for designing an integrated circuit having multiple voltage domains

Programmable array interconnect network

Method of connecting core I/O pins to backside chip I/O pads

Design structures, method and systems of powering on integrated circuit

Apparatus and method for improved SRAM device performance through double gate topology

Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits

System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology

System and method for manufacturing test of a physical layer transceiver

Structure for intrinsic RC power distribution for noise filtering of analog supplies

Digital to analog converter having fastpaths

Design structures of powering on integrated circuit

Design structures and systems involving digital to analog converters

Device and method to eliminate step response power supply perturbation

Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices

Method and circuit for testing a regulated power supply in an integrated circuit

Method of automatic latch insertion for testing application specific integrated circuits

Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

Apparatus for improved SRAM device performance through double gate topology

Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design

Low skew, power sequence independent CMOS receiver device

Process tolerant delay circuit

Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Transceiver for receiving and transmitting data over a network and method for testing the same

Structure and method for providing gate leakage isolation locally within analog circuits

Real-time adaptive voltage control of logic blocks

Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits

System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure

Transceiver for receiving and transmitting data over a network and method for testing the same

Intrinsic RC power distribution for noise filtering of analog supplies

Design structure to eliminate step response power supply perturbation

Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices

Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees

Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees

Intrinsic RC power distribution for noise filtering of analog supplies

System and method for balancing delay of signal communication paths through well voltage adjustment

Method and apparatus for reducing noise in a dynamic manner

System and method for control parameter re-centering in a controlled phase lock loop system

Low voltage head room detection for reliable start-up of self-biased analog circuits

Critical path redundant logic for mitigation of hardware across chip variation

Tunable capacitor

Method and apparatus for storing circuit calibration information

Testing integrated circuit designs containing multiple phase rotators

System and method for improved bitwrite capability in a field programmable memory array

BULZACCHELLI JOHN F

Dual-loop voltage regulator architecture with high DC accuracy and fast response time

CHU ALBERT M

Current leakage in RC ESD clamps

IADANZA JOSEPH A

Resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal