Inventor
CHUNG VICENTE ENRIQUE
US14 patents
Patents
14 patentsUS7469318B2Dec 23, 2008
System bus structure for large L2 cache array topology with different latency domains
IBM46 citations96
US7308558B2Dec 11, 2007
Multiprocessor data processing system having scalable data interconnect and data routing mechanism
IBM39 citations92
US6865695B2Mar 8, 2005
Robust system bus recovery
IBM20 citations92
US6581116B1Jun 17, 2003
Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system
IBM34 citations92
US6360297B1Mar 19, 2002
System bus read address operations with data ordering preference hint bits for vertical caches
IBM31 citations92
US7308536B2Dec 11, 2007
System bus read data transfers with data ordering control bits
IBM6 citations74
US6535957B1Mar 18, 2003
System bus read data transfers with bus utilization based data ordering
IBM9 citations74
US6487679B1Nov 26, 2002
Error recovery mechanism for a high-performance interconnect
IBM8 citations74
US6349360B1Feb 19, 2002
System bus read address operations with data ordering preference hint bits
IBM8 citations74
US8015358B2Sep 6, 2011
System bus structure for large L2 cache array topology with different latency domains
IBM1 citations63
US7526631B2Apr 28, 2009
Data processing system with backplane and processor books configurable to support both technical and commercial workloads
IBM6 citations63
US7007128B2Feb 28, 2006
Multiprocessor data processing system having a data routing mechanism regulated through control communication
IBM3 citations63
US6874063B1Mar 29, 2005
System bus read data transfers with data ordering control bits
IBM4 citations63
US7793048B2Sep 7, 2010
System bus structure for large L2 cache array topology with different latency domains
IBM0 citations52