Inventor
ASHAR PRANAV
US27 patents
⚠️ This page may combine multiple inventors who share the name “ASHAR PRANAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NEC CORP
9 patentsUS7383166B2Jun 3, 2008
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
NEC CORP86 citations98
US6745160B1Jun 1, 2004
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
NEC CORP115 citations98
US6975976B1Dec 13, 2005
Property specific testbench generation framework for circuit design validation by guided simulation
NEC CORP98 citations97
US6816825B1Nov 9, 2004
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
NEC CORP98 citations97
US6874135B2Mar 29, 2005
Method for design validation using retiming
NEC CORP36 citations92
US6728665B1Apr 27, 2004
SAT-based image computation with application in reachability analysis
NEC CORP34 citations92
US6651234B2Nov 18, 2003
Partition-based decision heuristics for SAT and image computation using SAT and BDDs
NEC CORP42 citations92
US7711525B2May 4, 2010
Efficient approaches for bounded model checking
NEC CORP18 citations84
US6662323B1Dec 9, 2003
Fast error diagnosis for combinational verification
NEC CORP16 citations84
NEC USA INC
7 patentsUS6163876ADec 19, 2000
Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow
NEC USA INC103 citations96
US6038392AMar 14, 2000
Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware
NEC USA INC79 citations95
US6496961B2Dec 17, 2002
Dynamic detection and removal of inactive clauses in SAT with application in image computation
NEC USA INC40 citations93
US6415430B1Jul 2, 2002
Method and apparatus for SAT solver architecture with very low synthesis and layout overhead
NEC USA INC42 citations91
US6247164B1Jun 12, 2001
Configurable hardware system implementing Boolean Satisfiability and method thereof
NEC USA INC39 citations91
US6223141B1Apr 24, 2001
Speeding up levelized compiled code simulation using netlist transformations
NEC USA INC14 citations74
US5748486AMay 5, 1998
Breadth-first manipulation of binary decision diagrams
NEC USA INC16 citations67
NEC LAB AMERICA INC
5 patentsUS7019674B2Mar 28, 2006
Content-based information retrieval architecture
NEC LAB AMERICA INC91 citations96
US7742907B2Jun 22, 2010
Iterative abstraction using SAT-based BMC with proof analysis
NEC LAB AMERICA INC22 citations92
US7386818B2Jun 10, 2008
Efficient modeling of embedded memories in bounded memory checking
NEC LAB AMERICA INC10 citations84
US7203917B2Apr 10, 2007
Efficient distributed SAT and SAT-based distributed bounded model checking
NEC LAB AMERICA INC7 citations74
US7305637B2Dec 4, 2007
Efficient SAT-based unbounded symbolic model checking
NEC LAB AMERICA INC4 citations62