Inventor

CAIN HAROLD W

US7 patents

⚠️ This page may combine multiple inventors who share the name “CAIN HAROLD W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

5 patents

US7793049B2Sep 7, 2010

Mechanism for data cache replacement based on region policies

IBM28 citations88

US9626256B2Apr 18, 2017

Determining failure context in hardware transactional memories

IBM0 citations51

US9268599B2Feb 23, 2016

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

IBM0 citations49

US7516309B2Apr 7, 2009

Method and apparatus for conditional memory ordering

IBM0 citations48

US7971039B2Jun 28, 2011

Conditional memory ordering

IBM0 citations44

BLAINEY ROBERT J

1 patent

US9268598B2Feb 23, 2016

Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

BLAINEY ROBERT J0 citations51

CAIN HAROLD W

1 patent

US9619345B2Apr 11, 2017

Apparatus for determining failure context in hardware transactional memories

CAIN HAROLD W1 citations45