Inventor
MAY MICHAEL DAVID
GB28 patents
⚠️ This page may combine multiple inventors who share the name “MAY MICHAEL DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SGS THOMSON MICROELECTRONICS
12 patentsUS6356960B1Mar 12, 2002
Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port
SGS THOMSON MICROELECTRONICS118 citations98
US6564314B1May 13, 2003
Computer instruction compression
SGS THOMSON MICROELECTRONICS81 citations97
US6415344B1Jul 2, 2002
System and method for on-chip communication
SGS THOMSON MICROELECTRONICS73 citations96
US6414368B1Jul 2, 2002
Microcomputer with high density RAM on single chip
SGS THOMSON MICROELECTRONICS64 citations95
US6301657B1Oct 9, 2001
System and method for booting a computer
SGS THOMSON MICROELECTRONICS41 citations92
US6009508ADec 28, 1999
System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis
SGS THOMSON MICROELECTRONICS33 citations92
US6757759B1Jun 29, 2004
Microcomputer chips with interconnected address and data paths
SGS THOMSON MICROELECTRONICS9 citations74
US6697931B1Feb 24, 2004
System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry
SGS THOMSON MICROELECTRONICS11 citations74
US6549965B1Apr 15, 2003
Microcomputer with interrupt packets
SGS THOMSON MICROELECTRONICS8 citations74
US6449670B1Sep 10, 2002
Microcomputer with bit packets for interrupts, control and memory access
SGS THOMSON MICROELECTRONICS9 citations74
US6397325B1May 28, 2002
Microcomputer with packet translation for event packets and memory access packets
SGS THOMSON MICROELECTRONICS11 citations74
US6658514B1Dec 2, 2003
Interrupt and control packets for a microcomputer
SGS THOMSON MICROELECTRONICS4 citations63
XMOS LTD
8 patentsUS7676653B2Mar 9, 2010
Compact instruction set encoding
XMOS LTD21 citations92
US7958333B2Jun 7, 2011
Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
XMOS LTD9 citations84
US8347312B2Jan 1, 2013
Thread communications
XMOS LTD8 citations81
US7617386B2Nov 10, 2009
Scheduling thread upon ready signal set when port transfers data on trigger time activation
XMOS LTD9 citations81
US7962717B2Jun 14, 2011
Message routing scheme
XMOS LTD3 citations62
US7613909B2Nov 3, 2009
Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor
XMOS LTD6 citations60
US7948060B2May 24, 2011
Integrated circuit structure
XMOS LTD5 citations56
US9594720B2Mar 14, 2017
Interface between a bus and a inter-thread interconnect
XMOS LTD0 citations34
MAY MICHAEL D
8 patentsUS8224884B2Jul 17, 2012
Processor communication tokens
MAY MICHAEL D7 citations83
US8966488B2Feb 24, 2015
Synchronising groups of threads with dedicated hardware logic
MAY MICHAEL D8 citations81
US9367321B2Jun 14, 2016
Processor instruction set for controlling an event source to generate events used to schedule threads
MAY MICHAEL D5 citations72
US8219789B2Jul 10, 2012
Interface processor
MAY MICHAEL D3 citations62
US8185722B2May 22, 2012
Processor instruction set for controlling threads to respond to events
MAY MICHAEL D5 citations62
US8139601B2Mar 20, 2012
Token protocol
MAY MICHAEL D3 citations62
US8185719B2May 22, 2012
Message routing scheme for an array having a switch with address comparing component and message routing component
MAY MICHAEL D0 citations51
US8898438B2Nov 25, 2014
Processor architecture for use in scheduling threads in response to communication activity
MAY MICHAEL D0 citations41