Inventor

SELIGER FRANK

DE19 patents

⚠️ This page may combine multiple inventors who share the name “SELIGER FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SELIGER FRANK

IBM

Method and system for securely handling information between two information processing devices

Election system enabling coercion-free remote voting

Election system enabling coercion-free remote voting

System, method and program product for anonymous transfer of messages

MUNETOH SEIJI

Information processing apparatus, a server apparatus, a method of an information processing apparatus, a method of a server apparatus, and an apparatus executable program

Information processing apparatus, a server apparatus, a method of an information processing apparatus, a method of a server apparatus, and an apparatus executable process

GLOBALFOUNDRIES INC

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition

ADVANCED MICRO DEVICES INC

Semiconductor substrate thinning method for manufacturing thinned die

Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure

HEINRICH JENS

Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors

Cap removal in a high-k metal gate electrode structure by using a sacrificial fill material

RICHTER RALF

Cap layer removal in a high-K metal gate stack by using an etch process

GLOBALFOUNDARIES INC

Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

KRONHOLZ STEPHAN

Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material

BEYER SVEN

Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure

FROHBERG KAI

Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer

LEHR MATTHIAS

Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques

LENSKI MARKUS

Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device