Inventor

TADAYON POOYA

US64 patents

⚠️ This page may combine multiple inventors who share the name “TADAYON POOYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TADAYON POOYA

INTEL CORP

Electrical energy-generating heat sink system and method of using same to recharge an energy storage device

Electrical energy-generating heat sink system and method of using same to recharge an energy storage device

Chip package enabling increased input/output density

Hyperchip

Electrical energy-generating system and devices and methods related thereto

Device, method and system for optical communication with a waveguide structure and an integrated optical coupler of a photonic integrated circuit chip

Hyperchip

Liquid cooling through conductive interconnect

High density and fine pitch interconnect structures in an electric test apparatus

Vacuum modulated two phase cooling loop efficiency and parallelism enhancement

Slip-plane MEMs probe for high-density and fine pitch interconnects

Selective recess of interconnects for probing hybrid bond devices

Slip-plane MEMS probe for high-density and fine pitch interconnects

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Low force liquid metal interconnect solutions

Interconnects including liquid metal

Converged test platforms and processes for class and system testing of integrated circuits

Photonic integrated circuit to glass substrate alignment through dual cylindrical lens

Hyperchip

Through-substrate optical vias

Coreless electronic substrates having embedded inductors

Double-sided substrate with cavities for direct die-to-die interconnect

Hybrid thermal interface material (TIM) with reduced 3D thermal resistance

Hyperchip

Chevron interconnect for very fine pitch probing

Hyperchip

Vacuum modulated two phase cooling loop performance enhancement

Method and apparatus to develop lithographically defined high aspect ratio interconnects

Double-sided substrate with cavities for direct die-to-die interconnect

Thermal spreading management of 3D stacked integrated circuits

Chevron interconnect for very fine pitch probing

High density and fine pitch interconnect structures in an electric test apparatus

Method and apparatus to develop lithographically defined high aspect ratio interconnects

Thermal spreading management of 3D stacked integrated circuits

Photonic integrated circuit to glass substrate alignment through integrated cylindrical lens and waveguide structure

Heterogenous socket contact for electrical and mechanical performance scaling in a microelectronic package

Die last and waveguide last architecture for silicon photonic packaging

Low force liquid metal interconnect solutions

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Thermally enhanced silicon back end layers for improved thermal performance

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Sloped metal features for cooling hotspots in stacked-die packages

Liquid metal interconnect for modular package server architecture

Multi-member test probe structure

Multi-member test probe structure

Reworkable zero-force insertion electrical optical package socket and method

Directly impinging pressure modulated spray cooling and methods of target temperature control

Technologies for chip-to-chip optical data transfer background

Device, method and system for optical communication with a photonic integrated circuit chip and a transverse oriented lens structure

CRIPPEN WARREN S

Increasing current carrying capability through direct liquid cooling of test contacts