Inventor
SURENDRAN SUDHAKAR
IN15 patents
⚠️ This page may combine multiple inventors who share the name “SURENDRAN SUDHAKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TEXAS INSTRUMENTS INC
11 patentsUS11334701B2May 17, 2022
Method for comprehensive integration verification of mixed-signal circuits
TEXAS INSTRUMENTS INC2 citations71
US10949594B2Mar 16, 2021
Method for comprehensive integration verification of mixed-signal circuits
TEXAS INSTRUMENTS INC3 citations71
US10489538B2Nov 26, 2019
Method for comprehensive integration verification of mixed-signal circuits
TEXAS INSTRUMENTS INC2 citations71
US12181974B2Dec 31, 2024
Techniques for peripheral utilization metrics collection and reporting
TEXAS INSTRUMENTS INC0 citations62
US12321674B2Jun 3, 2025
Hierarchical CDC and RDC verification
TEXAS INSTRUMENTS INC0 citations61
US12197840B2Jan 14, 2025
Techniques for modeling and verification of convergence for hierarchical domain crossings
TEXAS INSTRUMENTS INC0 citations61
US11775718B2Oct 3, 2023
Methods and apparatus to simulate metastability for circuit design verification
TEXAS INSTRUMENTS INC0 citations61
US11669668B2Jun 6, 2023
Method for comprehensive integration verification of mixed-signal circuits
TEXAS INSTRUMENTS INC0 citations61
US11531798B2Dec 20, 2022
Methods and apparatus to simulate metastability for circuit design verification
TEXAS INSTRUMENTS INC1 citations61
US12510920B2Dec 30, 2025
Managing clock trigger signals for asynchronous clock domains
TEXAS INSTRUMENTS INC0 citations58
US12375070B2Jul 29, 2025
Dynamic control of a multi-trim oscillator
TEXAS INSTRUMENTS INC0 citations58
SAJAYAN SAJISH
3 patentsUS8112652B2Feb 7, 2012
Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bank
SAJAYAN SAJISH12 citations90
US8078897B2Dec 13, 2011
Power management in federated/distributed shared memory architecture
SAJAYAN SAJISH2 citations60
US8117398B2Feb 14, 2012
Prefetch termination at powered down memory bank boundary in shared memory controller
SAJAYAN SAJISH0 citations49