P

Inventor

GHOSE SUSMITA

US23 patents
⚠️ This page may combine multiple inventors who share the name “GHOSE SUSMITA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

15 patents
US12272727B2Apr 8, 2025

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures

INTEL CORP2 citations74
US12243875B2Mar 4, 2025

Forksheet transistors with dielectric or conductive spine

INTEL CORP2 citations74
US11527612B2Dec 13, 2022

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

INTEL CORP6 citations74
US11990513B2May 21, 2024

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures

INTEL CORP2 citations72
US11923370B2Mar 5, 2024

Forksheet transistors with dielectric or conductive spine

INTEL CORP2 citations72
US11532706B2Dec 20, 2022

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures

INTEL CORP3 citations72
US11532734B2Dec 20, 2022

Gate-all-around integrated circuit structures having germanium nanowire channel structures

INTEL CORP3 citations71
US12206027B2Jan 21, 2025

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing

INTEL CORP0 citations62
US11769836B2Sep 26, 2023

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing

INTEL CORP1 citations62
US11978784B2May 7, 2024

Gate-all-around integrated circuit structures having germanium nanowire channel structures

INTEL CORP0 citations61
US12484266B2Nov 25, 2025

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

INTEL CORP0 citations59
US11469299B2Oct 11, 2022

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

INTEL CORP0 citations59
US12557340B2Feb 17, 2026

Cladding and condensation for strained semiconductor nanoribbons

INTEL CORP0 citations51
US12543351B2Feb 3, 2026

Enriched semiconductor nanoribbons for producing intrinsic compressive strain

INTEL CORP0 citations51
US12414366B2Sep 9, 2025

Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation

INTEL CORP0 citations50

ALPHONSO INC

6 patents

HEWLETT PACKARD ENTPR DEV LP

1 patent

ANOKI INC

1 patent