Inventor

PENUMATCHA ASHISH VERMA

US38 patents

Patents

38 patents

US11646374B2May 9, 2023

Ferroelectric transistors to store multiple states of resistances for memory cells

INTEL CORP2 citations73

US11605624B2Mar 14, 2023

Encapsulation for transition metal dichalcogenide nanosheet transistor and methods of fabrication

INTEL CORP1 citations63

US12349442B2Jul 1, 2025

Thin film transistors having semiconductor structures integrated with 2D channel materials

INTEL CORP0 citations62

US12278289B2Apr 15, 2025

TMD inverted nanowire integration

INTEL CORP0 citations62

US12224309B2Feb 11, 2025

Capacitors with built-in electric fields

INTEL CORP0 citations62

US12176388B2Dec 24, 2024

Transition metal dichalcogenide nanowires and methods of fabrication

INTEL CORP0 citations62

US12125893B2Oct 22, 2024

Piezo-resistive transistor based resonator with anti-ferroelectric gate dielectric

INTEL CORP0 citations62

US12113117B2Oct 8, 2024

Piezo-resistive transistor based resonator with ferroelectric gate dielectric

INTEL CORP0 citations62

US11935956B2Mar 19, 2024

TMD inverted nanowire integration

INTEL CORP0 citations62

US11908950B2Feb 20, 2024

Charge-transfer spacers for stacked nanoribbon 2D transistors

INTEL CORP0 citations62

US11653502B2May 16, 2023

FeFET with embedded conductive sidewall spacers and process for forming the same

INTEL CORP0 citations62

US11646356B2May 9, 2023

Piezo-resistive transistor based resonator with anti-ferroelectric gate dielectric

INTEL CORP0 citations62

US11637191B2Apr 25, 2023

Piezo-resistive transistor based resonator with ferroelectric gate dielectric

INTEL CORP0 citations62

US11532439B2Dec 20, 2022

Ultra-dense ferroelectric memory with self-aligned patterning

INTEL CORP1 citations62

US10886265B2Jan 5, 2021

Integrated circuit device with a two-dimensional semiconductor material and a dielectric material that includes fixed charges

INTEL CORP0 citations62

US12432976B2Sep 30, 2025

Thin film transistors having strain-inducing structures integrated with 2D channel materials

INTEL CORP0 citations61

US12369382B2Jul 22, 2025

Integrated circuit structures with graphene contacts

INTEL CORP0 citations61

US12266720B2Apr 1, 2025

Transistors with monocrystalline metal chalcogenide channel materials

INTEL CORP0 citations61

US11901400B2Feb 13, 2024

MFM capacitor and process for forming such

INTEL CORP0 citations61

US11769789B2Sep 26, 2023

MFM capacitor with multilayered oxides and metals and processes for forming such

INTEL CORP0 citations61

US11640984B2May 2, 2023

Transistor device with (anti)ferroelectric spacer structures

INTEL CORP0 citations61

US12588257B2Mar 24, 2026

2D layered gate oxide

INTEL CORP0 citations60

US12406713B2Sep 2, 2025

Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor

INTEL CORP0 citations59

US12166122B2Dec 10, 2024

Field-effect transistor (FET) with self-aligned ferroelectric capacitor and methods of fabrication

INTEL CORP0 citations52

US10886286B2Jan 5, 2021

Vertical memory control circuitry located in interconnect layers

INTEL CORP0 citations52

US12349438B2Jul 1, 2025

Contact gating for 2D field effect transistors

INTEL CORP0 citations51

US12324204B2Jun 3, 2025

Transistors including two-dimensional materials

INTEL CORP0 citations51

US12266712B2Apr 1, 2025

Transition metal dichalcogenide nanosheet transistors and methods of fabrication

INTEL CORP0 citations51

US12125895B2Oct 22, 2024

Transition metal dichalcogenide (TMD) layer stack for transistor applications and methods of fabrication

INTEL CORP0 citations51

US12575111B2Mar 10, 2026

Back-end-of-line 2D memory cell

INTEL CORP0 citations50

US12310101B2May 20, 2025

Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

INTEL CORP0 citations50

US11980037B2May 7, 2024

Memory cells with ferroelectric capacitors separate from transistor gate stacks

INTEL CORP0 citations50

US11616130B2Mar 28, 2023

Transistor device with variously conformal gate dielectric layers

INTEL CORP0 citations50

US11742407B2Aug 29, 2023

Multilayer high-k gate dielectric for a high performance logic transistor

INTEL CORP0 citations49

US12484457B2Nov 25, 2025

Differentially programmable magnetic tunnel junction device and system including same

INTEL CORP0 citations48

PENUMATCHA ASHISH VERMA

Patents

Ferroelectric transistors to store multiple states of resistances for memory cells

Ferroelectric resonator

Relaxor ferroelectric capacitors and methods of fabrication

Stacked 2D CMOS with inter metal layers

Encapsulation for transition metal dichalcogenide nanosheet transistor and methods of fabrication

Thin film transistors having semiconductor structures integrated with 2D channel materials

TMD inverted nanowire integration

Capacitors with built-in electric fields

Transition metal dichalcogenide nanowires and methods of fabrication

Piezo-resistive transistor based resonator with anti-ferroelectric gate dielectric

Piezo-resistive transistor based resonator with ferroelectric gate dielectric

TMD inverted nanowire integration

Charge-transfer spacers for stacked nanoribbon 2D transistors

FeFET with embedded conductive sidewall spacers and process for forming the same

Piezo-resistive transistor based resonator with anti-ferroelectric gate dielectric

Piezo-resistive transistor based resonator with ferroelectric gate dielectric

Ultra-dense ferroelectric memory with self-aligned patterning

Integrated circuit device with a two-dimensional semiconductor material and a dielectric material that includes fixed charges

Thin film transistors having strain-inducing structures integrated with 2D channel materials

Integrated circuit structures with graphene contacts

Transistors with monocrystalline metal chalcogenide channel materials

MFM capacitor and process for forming such

MFM capacitor with multilayered oxides and metals and processes for forming such

Transistor device with (anti)ferroelectric spacer structures

2D layered gate oxide

Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor

Field-effect transistor (FET) with self-aligned ferroelectric capacitor and methods of fabrication

Vertical memory control circuitry located in interconnect layers

Contact gating for 2D field effect transistors

Transistors including two-dimensional materials

Transition metal dichalcogenide nanosheet transistors and methods of fabrication

Transition metal dichalcogenide (TMD) layer stack for transistor applications and methods of fabrication

Back-end-of-line 2D memory cell

Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

Memory cells with ferroelectric capacitors separate from transistor gate stacks

Transistor device with variously conformal gate dielectric layers

Multilayer high-k gate dielectric for a high performance logic transistor

Differentially programmable magnetic tunnel junction device and system including same