Inventor
KANG JUN SUNG
US17 patents
Patents
17 patentsUS11342411B2May 24, 2022
Cavity spacer for nanowire transistors
INTEL CORP7 citations84
US11205715B2Dec 21, 2021
Self-aligned nanowire
INTEL CORP2 citations73
US11929396B2Mar 12, 2024
Cavity spacer for nanowire transistors
INTEL CORP2 citations72
US11404578B2Aug 2, 2022
Dielectric isolation layer between a nanowire transistor and a substrate
INTEL CORP3 citations72
US10672868B2Jun 2, 2020
Methods of forming self aligned spacers for nanowire device structures
INTEL CORP4 citations72
US11869891B2Jan 9, 2024
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process
INTEL CORP2 citations71
US11715787B2Aug 1, 2023
Self-aligned nanowire
INTEL CORP0 citations62
US10944006B2Mar 9, 2021
Geometry tuning of fin based transistor
INTEL CORP0 citations62
US12349394B2Jul 1, 2025
Dielectric isolation layer between a nanowire transistor and a substrate
INTEL CORP0 citations61
US12328905B2Jun 10, 2025
Cavity spacer for nanowire transistors
INTEL CORP0 citations61
US12302632B2May 13, 2025
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process
INTEL CORP0 citations61
US11901458B2Feb 13, 2024
Dielectric isolation layer between a nanowire transistor and a substrate
INTEL CORP0 citations61
US11069795B2Jul 20, 2021
Transistors with channel and sub-channel regions with distinct compositions and dimensions
INTEL CORP1 citations61
US12453115B2Oct 21, 2025
Nanowire transistor structure and method of shaping
INTEL CORP0 citations59
US11869973B2Jan 9, 2024
Nanowire transistor structure and method of shaping
INTEL CORP0 citations59
US11276691B2Mar 15, 2022
Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths
INTEL CORP0 citations52
US10516021B2Dec 24, 2019
Reduced leakage transistors with germanium-rich channel regions
INTEL CORP0 citations52