Inventor

LEE YONG MENG

US37 patents

⚠️ This page may combine multiple inventors who share the name “LEE YONG MENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE YONG MENG

CHARTERED SEMICONDUCTOR MFG

Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding

Selective salicide process by reformation of silicon nitride sidewall spacers

Method of forming double-gate semiconductor-on-insulator (SOI) transistors

Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance

Method to enhance device performance with selective stress relief

Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance

Composite stress spacer

Method for forming damascene dual gate for improved oxide uniformity and control

Method to enhance device performance with selective stress relief

Selective salicide process by reformation of silicon nitride sidewall spacers

Double-gated silicon-on-insulator (SOI) transistors with corner rounding

Method of patterning gate electrode conductor with ultra-thin gate oxide

Spacer-less low-k dielectric processes

GLOBALFOUNDRIES INC

Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device

Forming self-aligned NiSi placement with improved performance and yield

Forming a gate by depositing a thin barrier layer on a titanium nitride cap

Using sacrificial oxide layer for gate length tuning and resulting device

Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection

Depositing an etch stop layer before a dummy cap layer to improve gate performance

IBM

Method and apparatus for post silicide spacer removal

Threshold voltage improvement employing fluorine implantation and adjustment oxide layer

Silicided polysilicon spacer for enhanced contact area

Post-silicide spacer removal

POET TECH INC

Structure and method for testing of PIC with an upturned mirror

Structure and method for testing of PIC with an upturned mirror

Structure and method for testing of PIC with an upturned mirror

GLOBALFOUNDRIES SG PTE LTD

Method of manufacture of an integrated circuit system with self-aligned isolation structures

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Integrated circuit having a plurality of MOSFET devices

TEO LEE WEE

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

INFINEON TECHNOLOGIES AG

Method of implanting a non-dopant atom into a semiconductor device

LEE YONG MENG

Spacer-less low-K dielectric processes

CHEN XIANGDONG

Balancing NFET and PFET performance using straining layers

PARK JAE-EUN

Spacer protection and electrical connection for array device