Inventor

HASHEMI POUYA

US586 patents

⚠️ This page may combine multiple inventors who share the name “HASHEMI POUYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HASHEMI POUYA

IBM

Stacked complementary FETs featuring vertically stacked horizontal nanowires

Fabrication of nano-sheet transistors with different threshold voltages

Gate-all-around nanowire MOSFET and method of formation

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

Stacked field-effect transistors (FETs) with shared and non-shared gates

Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance

Contact formation to 3D monolithic stacked FinFETs

Fabrication of strained vertical P-type field effect transistors by bottom condensation

Replacement III-V or germanium nanowires by unilateral confined epitaxial growth

Multiple gate length vertical field-effect-transistors

Channel-last replacement metal-gate vertical field effect transistor

Vertical transistor with air gap spacers

Dual work function integration for stacked FinFET

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

Gate-all-around nanowire MOSFET and method of formation

I/O device for gate-all-around transistors

Lateral bipolar junction transistor with controlled junction

Multiple dielectrics for gate-all-around transistors

Full air-gap spacers for gate-all-around nanosheet field effect transistors

Vertically stacked NFETS and PFETS with gate-all-around structure

Enhanced field bipolar resistive RAM integrated with FDSOI technology

Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness

High-density field-enhanced ReRAM integrated with vertical transistors

Nano-sheet transistors with different threshold voltages

Diode connected vertical transistor

Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures

Tight pitch inverter using vertical transistors

Dual strained nanosheet CMOS and methods for fabricating

Tapered vertical FET having III-V channel

Floating gate memory in a channel last vertical FET flow

Vertical floating gate memory with variable channel doping profile

Co-fabrication of vertical diodes and fin field effect transistors on the same substrate

Vertical field effect transistor with undercut buried insulating layer to improve contact resistance

High density programmable e-fuse co-integrated with vertical FETs

Lateral bipolar junction transistor with abrupt junction and compound buried oxide

Vertical transistors having different gate lengths

Self-aligned sigma extension regions for vertical transistors

III-V vertical field effect transistors with tunable bandgap source/drain regions

Nanosheet CMOS with hybrid orientation

Heterogeneous source drain region and extension region

Method to form stacked germanium nanowires and stacked III-V nanowires

Stacked nanowires with multi-threshold voltage solution for pFETs

Stacked nanosheets by aspect ratio trapping

Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy

Highly scaled tunnel FET with tight pitch and method to fabricate same

Nanowire device with improved epitaxy

Nanowire transistor structures with merged source/drain regions using auxiliary pillars

Vertical transistor pass gate device

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Contact formation for stacked FinFETs