Inventor

TEIG STEVEN L

US137 patents

⚠️ This page may combine multiple inventors who share the name “TEIG STEVEN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEIG STEVEN L

PERCEIVE CORP

Splitting neural network filters for implementation by neural network inference circuit

Computation of neural network node by neural network inference circuit

Reduced dot product computation circuit

Probabilistic loss function for training network with triplets

Compiler for implementing memory shutdown for neural network implementation configuration

Encoding of weight values stored on neural network inference circuit

Preventing overfitting of hyperparameters during training of network

Storage of input values within core of neural network inference circuit

Neural network inference circuit employing dynamic memory sleep

Weight value decoder of neural network inference circuit

Video denoising using neural networks with spatial and temporal features

Compiler for optimizing number of cores used to implement neural network

Optimizing global sparsity for neural network

Decomposition of ternary weight tensors

Compiler for optimizing filter sparsity for neural network implementation configuration

Replication of neural network layers

Write cache for neural network inference circuit

Neural network inference circuit read controller with multiple operational modes

Training sparse networks with discrete weight values

Iterative transfer of machine-trained network inputs from validation set to training set

Input value cache for temporarily storing input values

Non-dot product computations on neural network inference circuit

Mitigating overfitting in training machine trained networks

Loss-aware replication of neural network layers

Training network to minimize worst-case error

Computation of neural network node with large input values

Control circuits for neural network inference circuit

XCELSIS CORP

Three dimensional circuit implementing machine trained network

Stacked IC structure with system level wiring on multiple sides of the IC die

3D chip with shared clock distribution network

Self repairing neural network

Three dimensional chip structure implementing machine trained network

3D compute circuit with high density Z-axis interconnects

3D chip sharing power circuit

3D Compute circuit with high density z-axis interconnects

3D processor

Time borrowing between layers of a three dimensional chip stack

3D chip sharing data bus circuit

3D chip sharing power interconnect layer

3D chip sharing data bus

3D chip with shielded clock lines

3D chip sharing clock interconnect layer

Stacked IC structure with system level wiring on multiple sides of the IC die

Direct-bonded native interconnects and active base die

Direct-bonded native interconnects and active base die

Face-to-face mounted IC dies with orthogonal top interconnect layers

ADEIA SEMICONDUCTOR INC

Device disaggregation for improved performance

3D chip with shared clock distribution network

(unassigned)

Computer graphics system for selectively modelling molecules and investigating the chemical and physical properties thereof

MCC MOLECULAR SIMULATIONS

Computer graphics system for selectively modelling molecules and investigating the chemical and physical properties thereof