Inventor
HAYASHI TERUMINE
JP9 patents
Patents
9 patentsUS5200908AApr 6, 1993
Placement optimizing method/apparatus and apparatus for designing semiconductor devices
HITACHI LTD62 citations95
US5144563ASep 1, 1992
Method and apparatus for optimizing element placement and method and apparatus for deciding the optimal element placement
HITACHI LTD60 citations95
US5657242AAug 12, 1997
Method of determining routes for a plurality of wiring connections and a circuit board produced by such a method
HITACHI LTD148 citations92
US4701922AOct 20, 1987
Integrated circuit device
HITACHI LTD35 citations92
US4960724AOct 2, 1990
Method for deleting unused gates and method for manufacturing master-slice semiconductor integrated circuit device using the deleting method
HITACHI LTD32 citations88
US4613970ASep 23, 1986
Integrated circuit device and method of diagnosing the same
HITACHI LTD21 citations81
US5329532AJul 12, 1994
Logic circuit with additional circuit for carrying out delay test
HITACHI LTD18 citations73
US4956818ASep 11, 1990
Memory incorporating logic LSI and method for testing the same LSI
HITACHI LTD10 citations72
US4710930ADec 1, 1987
Method and apparatus for diagnosing a LSI chip
HITACHI LTD12 citations72