Inventor

LUNING SCOTT D

US43 patents

⚠️ This page may combine multiple inventors who share the name “LUNING SCOTT D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUNING SCOTT D

ADVANCED MICRO DEVICES INC

Dual damascene with a sacrificial via fill

Self aligned via dual damascene

Self aligned via dual damascene

Removable spacer technique

Subtractive dual damascene

Dual damascene with a protective mask for via etching

Method for obtaining a steep retrograde channel profile

Method of forming silicide layers over a plurality of semiconductor devices

Tilted counter-doped implant to sharpen halo profile

Angled halo implant tailoring using implant mask

Methods for post offset spacer clean for improved selective epitaxy silicon growth

Method for laterally peaked source doping profiles for better erase control in flash memory devices

Trench edge spacer formation

Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration

Subtractive dual damascene semiconductor device

Method for forming vertical profile of polysilicon gate electrodes

Integration scheme for constrained SEG growth on poly during raised S/D processing

Method of forming a semiconductor device

Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing

Method and system for gate stack reoxidation control

Stress enhanced CMOS circuits and methods for their fabrication

Semiconductor device and method for lowering miller capacitance for high-speed microprocessors

Semiconductor device and method of manufacturing a semiconductor device

Maintaining LDD series resistance of MOS transistors by retarding dopant segregation

Non-self-aligned side channel implants for flash memory cells

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Channel isolation using dielectric isolation structures

Method of forming a hard mask for halo implants

Method of reducing photoresist shadowing during angled implants

Gate re-masking for deeper source/drain co-implantation processes

Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors

Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting

Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects

Method of forming a gate electrode on a semiconductor device and a device incorporating same

GLOBALFOUNDRIES INC

Semiconductor device and method of manufacturing a semiconductor device

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

Simplified gate to source/drain region connections

MANN RANDY W

SRAM cell with individual electrical device threshold control

SRAM cell with individual electrical device threshold control

PEI GEN

CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer