Inventor

FEELEY PETER

US160 patents

⚠️ This page may combine multiple inventors who share the name “FEELEY PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FEELEY PETER

MICRON TECHNOLOGY INC

Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods

Identifying asynchronous power loss

Methods, devices, and systems for adjusting sensing voltages in devices

Voltage bin selection for blocks of a memory device after power up of the memory device

Cache management based on memory device over-provisioning

Trim setting determination on a memory device

Trim setting determination on a memory device

Configurable trim settings on a memory device

Selectable trim settings on a memory device

Trim setting determination on a memory device

Memory device with dynamic cache management

Selectable trim settings on a memory device

Garbage collection

Trim setting determination on a memory device

Redundant array of independent NAND for a three-dimensional memory array

Memory cell coupling compensation

Memory cell coupling compensation

Methods, devices, and systems for adjusting sensing voltages in devices

Object oriented memory in solid state devices

Methods, devices, and systems for adjusting sensing voltages in devices

Memory system controller

Block family-based error avoidance for memory devices

Voltage bin selection for blocks of a memory device after power up of the memory device

Managing voltage bin selection for blocks of a memory device

Configurable trim settings on a memory device

Selectable trim settings on a memory device

Managing error-handling flows in memory devices

Memory device with dynamic cache management

Voltage calibration scans to reduce memory device overhead

Voltage bin calibration based on a temporary voltage shift offset

Block family-based error avoidance for memory devices

Extended cross-temperature handling in a memory sub-system

Operation of mixed mode blocks

Memory device with dynamic cache management

Memory management

Memory device with dynamic storage mode control

Identifying asynchronous power loss

Memory management

Operation of mixed mode blocks

Identifying asynchronous power loss

Memory device with dynamic storage mode control

SHEN ZHENLEI

Methods, devices, and systems for dealing with threshold voltage change in memory devices

Methods, devices, and systems for dealing with threshold voltage change in memory devices

LEIBOWITZ ROBERT N

Memory system controller to manage wear leveling across a plurality of storage nodes

RADKE WILLIAM H

Determining and using soft data in memory devices and systems

SAKUI KOJI

Memory with three transistor memory cell device

GALBO NEAL A

Methods for controlling host memory access with memory devices and systems

FEELEY PETER

Object oriented memory in solid state devices

ABRAHAM MICHAEL M

Data signal mirroring

KAWAI KOICHI

Devices and methods of programming memory cells