Inventor
FURUYAMA TAKAAKI
JP32 patents
⚠️ This page may combine multiple inventors who share the name “FURUYAMA TAKAAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FUJITSU LTD
17 patentsUS6097658AAug 1, 2000
DRAM with reduced electric power consumption
FUJITSU LTD49 citations95
US6643758B2Nov 4, 2003
Flash memory capable of changing bank configuration
FUJITSU LTD21 citations92
US6310825B1Oct 30, 2001
Data writing method for semiconductor memory device
FUJITSU LTD50 citations92
US5909407AJun 1, 1999
Word line multi-selection circuit for a memory device
FUJITSU LTD38 citations92
US5787046AJul 28, 1998
Semiconductor memory device provided with block write function
FUJITSU LTD25 citations92
US5594699AJan 14, 1997
DRAM with reduced electric power consumption
FUJITSU LTD25 citations92
US6917541B2Jul 12, 2005
Nonvolatile semiconductor memory device
FUJITSU LTD28 citations91
US6879521B2Apr 12, 2005
Threshold voltage adjustment method of non-volatile semiconductor memory device and non-volatile semiconductor memory device
FUJITSU LTD10 citations74
US6490215B2Dec 3, 2002
Semiconductor memory device and refreshing method of semiconductor memory device
FUJITSU LTD11 citations74
US6128238AOct 3, 2000
Direct sensing semiconductor memory device
FUJITSU LTD11 citations74
US6462997B2Oct 8, 2002
Circuit for resetting a pair of data buses of a semiconductor memory device
FUJITSU LTD8 citations73
US4989182AJan 29, 1991
Dynamic random access memory having dummy word line for facilitating reset of row address latch
FUJITSU LTD17 citations71
US5708625AJan 13, 1998
Voltage level detector
FUJITSU LTD6 citations63
US7452771B2Nov 18, 2008
Method for fabricating a semiconductor device
FUJITSU LTD3 citations62
US6977411B2Dec 20, 2005
Semiconductor device comprising transistors having control gates and floating gate electrodes
FUJITSU LTD5 citations62
US6198680B1Mar 6, 2001
Circuit for resetting a pair of data buses of a semiconductor memory device
FUJITSU LTD2 citations62
US4932000AJun 5, 1990
Semiconductor memory device having pseudo row decoder
FUJITSU LTD5 citations62
SPANSION LLC
13 patentsUS7068555B2Jun 27, 2006
Semiconductor memory storage device and a redundancy control method therefor
SPANSION LLC12 citations84
US8023341B2Sep 20, 2011
Method and apparatus for address allotting and verification in a semiconductor device
SPANSION LLC4 citations74
US7415568B2Aug 19, 2008
Method and apparatus for initialization control in a non-volatile memory device
SPANSION LLC8 citations73
US7813154B2Oct 12, 2010
Method and apparatus for address allotting and verification in a semiconductor device
SPANSION LLC1 citations63
US7433219B2Oct 7, 2008
Method and apparatus for address allotting and verification in a semiconductor device
SPANSION LLC1 citations63
US7212443B2May 1, 2007
Non-volatile memory and write method of the same
SPANSION LLC6 citations63
US7061816B2Jun 13, 2006
Semiconductor memory storage device and its redundant method
SPANSION LLC5 citations63
US7889573B2Feb 15, 2011
Time reduction of address setup/hold time for semiconductor memory
SPANSION LLC3 citations62
US7321515B2Jan 22, 2008
Memory device and control method therefor
SPANSION LLC2 citations62
US7239548B2Jul 3, 2007
Method and apparatus for applying bias to a storage device
SPANSION LLC2 citations62
US7281180B2Oct 9, 2007
Memory system and test method therefor
SPANSION LLC0 citations52
US8031537B2Oct 4, 2011
Time reduction of address setup/hold time for semiconductor memory
SPANSION LLC0 citations51
US7808808B2Oct 5, 2010
Nonvolatile memory device having a plurality of memory blocks
SPANSION LLC0 citations51