P

Inventor

ZHENG TIEYU

US22 patents
⚠️ This page may combine multiple inventors who share the name “ZHENG TIEYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

19 patents
US7429182B1Sep 30, 2008

Socket assembly for securing socket body

INTEL CORP21 citations92
US6860652B2Mar 1, 2005

Package for housing an optoelectronic assembly

INTEL CORP18 citations92
US7176436B2Feb 13, 2007

Method and apparatus for manufacturing a transistor-outline (TO) can having a ceramic header

INTEL CORP11 citations84
US7695288B2Apr 13, 2010

Land grid array (LGA) socket with cells and method of fabrication and assembly

INTEL CORP17 citations83
US7479015B2Jan 20, 2009

Socket assembly that includes improved contact arrangement

INTEL CORP10 citations83
US7223629B2May 29, 2007

Method and apparatus for manufacturing a transistor-outline (TO) can having a ceramic header

INTEL CORP10 citations83
US7278859B1Oct 9, 2007

Extended package substrate

INTEL CORP10 citations82
US7604486B2Oct 20, 2009

Lateral force countering load mechanism for LGA sockets

INTEL CORP18 citations79
US7261572B2Aug 28, 2007

Self-balanced land grid array socket

INTEL CORP9 citations73
US7255496B2Aug 14, 2007

Package for housing an optoelectronic assembly

INTEL CORP5 citations73
US7524199B2Apr 28, 2009

Pick-and-place cap for socket assembly

INTEL CORP4 citations62
US7419383B2Sep 2, 2008

Self-balanced dual L-shaped socket

INTEL CORP4 citations62
US7255494B2Aug 14, 2007

Low-profile package for housing an optoelectronic assembly

INTEL CORP5 citations62
US7227248B2Jun 5, 2007

Stacked land grid array package

INTEL CORP3 citations62
US7201521B2Apr 10, 2007

Method and apparatus for manufacturing a transistor-outline (TO) can having a ceramic header

INTEL CORP2 citations62
US6992373B2Jan 31, 2006

Stacked land grid array package

INTEL CORP3 citations62
US7497696B2Mar 3, 2009

Socket for land grid array package

INTEL CORP2 citations61
US9312237B2Apr 12, 2016

Integrated circuit package with spatially varied solder resist opening dimension

INTEL CORP2 citations58
US7677902B2Mar 16, 2010

Extended package substrate

INTEL CORP0 citations51

ZHENG TIEYU

2 patents

TROBOUGH MARK B

1 patent