Inventor
HEINECK LARS
US22 patents
⚠️ This page may combine multiple inventors who share the name “HEINECK LARS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INFINEON TECHNOLOGIES AG
7 patentsUS7274060B2Sep 25, 2007
Memory cell array and method of forming the same
INFINEON TECHNOLOGIES AG16 citations84
US6919255B2Jul 19, 2005
Semiconductor trench structure
INFINEON TECHNOLOGIES AG16 citations84
US7094674B2Aug 22, 2006
Method for production of contacts on a wafer
INFINEON TECHNOLOGIES AG13 citations81
US6916721B2Jul 12, 2005
Method for fabricating a trench capacitor with an insulation collar
INFINEON TECHNOLOGIES AG11 citations72
US7018781B2Mar 28, 2006
Method for fabricating a contact hole plane in a memory module
INFINEON TECHNOLOGIES AG9 citations69
US7087492B2Aug 8, 2006
Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate
INFINEON TECHNOLOGIES AG3 citations62
US7314803B2Jan 1, 2008
Method for producing a semiconductor structure
INFINEON TECHNOLOGIES AG0 citations45
MICRON TECHNOLOGY INC
4 patentsUS9881924B2Jan 30, 2018
Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same
MICRON TECHNOLOGY INC17 citations94
US10566332B2Feb 18, 2020
Semiconductor devices
MICRON TECHNOLOGY INC11 citations85
US10163909B2Dec 25, 2018
Methods for fabricating a semiconductor memory device
MICRON TECHNOLOGY INC6 citations84
US8361856B2Jan 29, 2013
Memory cells, arrays of memory cells, and methods of forming memory cells
MICRON TECHNOLOGY INC6 citations83
NANYA TECHNOLOGY CORP
4 patentsUS9691773B2Jun 27, 2017
Silicon buried digit line access device and method of forming the same
NANYA TECHNOLOGY CORP8 citations84
US9070584B2Jun 30, 2015
Buried digitline (BDL) access device and memory array
NANYA TECHNOLOGY CORP2 citations63
US9263317B2Feb 16, 2016
Method of forming buried word line structure
NANYA TECHNOLOGY CORP2 citations62
US9012330B2Apr 21, 2015
Method for semiconductor cross pitch doubled patterning process
NANYA TECHNOLOGY CORP2 citations62