Inventor

PIRY FREDERIC CLAUDE MARIE

FR34 patents

⚠️ This page may combine multiple inventors who share the name “PIRY FREDERIC CLAUDE MARIE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PIRY FREDERIC CLAUDE MARIE

ADVANCED RISC MACH LTD

Processing activity masking in a data processing system

Processing activity masking in a data processing system

Apparatus and method for controlling allocation of data into a cache storage

Branch target address provision

Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit

Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation

Speculative data value usage

Apparatus and method for controlling allocation of instructions into an instruction cache storage

Data processing apparatus and method for performing load-exclusive and store-exclusive operations

Selective prediction based on correlation between a given instruction and a subset of a set of monitored instructions ordinarily used to generate predictions for that given instruction

Speculative side-channel hint instruction

Apparatus and method for performing branch prediction

Controlling use of data determined by a resolve-pending speculative operation

Encoding of input to storage circuitry

Selective suppression of register renaming

Execution of instructions within a data processing apparatus having a plurality of processing units

Executing variable length instructions stored within a plurality of discrete memory address regions

Debug circuitry

Apparatus and method for predicting source operand values and optimized processing of instructions

Task dispatch

Tracking speculative data caching

Apparatus and method for prefetching data items

Cache control in presence of speculative read operations

Apparatus and method for mapping architectural registers to physical registers

Technique for training a prediction apparatus

Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction

Shared unit instruction execution

Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry

PIRY FREDERIC CLAUDE MARIE

Handling of write access requests to shared memory in a data processing apparatus

Limiting certain processing activities as error rate probability rises

Apparatus and method for mapping architectural registers to physical registers

Recovering from exceptions and timing errors

SCHON GUILLAUME

Error recovery in a data processing apparatus

Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution