Inventor
CAIA JEAN-MICHEL
US24 patents
⚠️ This page may combine multiple inventors who share the name “CAIA JEAN-MICHEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
14 patentsUS6944728B2Sep 13, 2005
Interleaving memory access
INTEL CORP18 citations92
US7298744B1Nov 20, 2007
Method and apparatus for centralized processing of contiguously and virtually concatenated payloads
INTEL CORP10 citations83
US7061867B2Jun 13, 2006
Rate-based scheduling for packet applications
INTEL CORP12 citations83
US6892284B2May 10, 2005
Dynamic memory allocation for assigning partitions to a logical port from two groups of un-assigned partitions based on two threshold values
INTEL CORP15 citations83
US7583599B1Sep 1, 2009
Transporting stream client signals via packet interface using GFP mapping
INTEL CORP17 citations79
US7295564B2Nov 13, 2007
Virtual output queue (VoQ) management method and apparatus
INTEL CORP9 citations73
US7352777B2Apr 1, 2008
Data framer
INTEL CORP3 citations62
US7154853B2Dec 26, 2006
Rate policing algorithm for packet flows
INTEL CORP3 citations62
US7065628B2Jun 20, 2006
Increasing memory access efficiency for packet applications
INTEL CORP2 citations62
US7656891B1Feb 2, 2010
Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads
INTEL CORP3 citations60
US7525977B1Apr 28, 2009
Control mechanism for mapping cells and packets
INTEL CORP3 citations60
US7508830B1Mar 24, 2009
Method and apparatus differential delay compensation processing of virtually concatenated data
INTEL CORP6 citations60
US7460545B1Dec 2, 2008
Enhanced SDRAM bandwidth usage and memory management for TDM traffic
INTEL CORP2 citations58
US7564777B2Jul 21, 2009
Techniques for group alarm indication signal generation and clearing
INTEL CORP1 citations51