Inventor
OU TSONG-HUA
TW40 patents
⚠️ This page may combine multiple inventors who share the name “OU TSONG-HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
14 patentsUS9026971B1May 5, 2015
Multi-patterning conflict free integrated circuit design
TAIWAN SEMICONDUCTOR MFG CO LTD26 citations92
US9852908B2Dec 26, 2017
Methods for integrated circuit design and fabrication
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations84
US9380709B2Jun 28, 2016
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations84
US10410863B2Sep 10, 2019
Methods for integrated circuit design and fabrication
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US12438000B2Oct 7, 2025
Methods for integrated circuit design and fabrication
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations63
US10930505B2Feb 23, 2021
Methods for integrated circuit design and fabrication
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations63
US9281273B1Mar 8, 2016
Designed-based interconnect structure in semiconductor structure
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations63
US12013643B2Jun 18, 2024
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11429028B2Aug 30, 2022
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10509322B2Dec 17, 2019
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9754881B2Sep 5, 2017
Designed-based interconnect structure in semiconductor structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9524939B2Dec 20, 2016
Multiple edge enabled patterning
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9478540B2Oct 25, 2016
Adaptive fin design for FinFETs
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
US9262577B2Feb 16, 2016
Layout method and system for multi-patterning integrated circuits
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
TAIWAN SEMICONDUCTOR MFG
10 patentsUS8001494B2Aug 16, 2011
Table-based DFM for accurate post-layout analysis
TAIWAN SEMICONDUCTOR MFG16 citations92
US7783999B2Aug 24, 2010
Electrical parameter extraction for integrated circuit design
TAIWAN SEMICONDUCTOR MFG23 citations92
US9176373B2Nov 3, 2015
System and method for decomposition of a single photoresist mask pattern into 3 photoresist mask patterns
TAIWAN SEMICONDUCTOR MFG11 citations84
US8037575B2Oct 18, 2011
Method for shape and timing equivalent dimension extraction
TAIWAN SEMICONDUCTOR MFG17 citations83
US8372742B2Feb 12, 2013
Method, system, and apparatus for adjusting local and global pattern density of an integrated circuit design
TAIWAN SEMICONDUCTOR MFG14 citations82
US9390223B2Jul 12, 2016
Method of determining whether a layout is colorable
TAIWAN SEMICONDUCTOR MFG2 citations63
US9362119B2Jun 7, 2016
Methods for integrated circuit design and fabrication
TAIWAN SEMICONDUCTOR MFG2 citations63
US9026957B2May 5, 2015
Method of defining an intensity selective exposure photomask
TAIWAN SEMICONDUCTOR MFG1 citations62
US8806392B2Aug 12, 2014
Distinguishable IC patterns with encoded information
TAIWAN SEMICONDUCTOR MFG2 citations62
US9287125B2Mar 15, 2016
Multiple edge enabled patterning
TAIWAN SEMICONDUCTOR MFG0 citations52
CHENG YING-CHOU
5 patentsUS8527918B2Sep 3, 2013
Target-based thermal design using dummy insertion for semiconductor devices
CHENG YING-CHOU11 citations83
US8332797B2Dec 11, 2012
Parameterized dummy cell insertion for process enhancement
CHENG YING-CHOU8 citations83
US8745554B2Jun 3, 2014
Practical approach to layout migration
CHENG YING-CHOU8 citations82
US8219951B2Jul 10, 2012
Method of thermal density optimization for device and process enhancement
CHENG YING-CHOU5 citations61
US8806386B2Aug 12, 2014
Customized patterning modulation and optimization
CHENG YING-CHOU0 citations50