Inventor

HOU YUAN-TE

TW77 patents

⚠️ This page may combine multiple inventors who share the name “HOU YUAN-TE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOU YUAN-TE

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device with reduced leakage current

Rule checking for multiple patterning technology

Non-hierarchical metal layers for integrated circuits

Cell layout design and method

Method and system for replacing a pattern in a layout

Integrated circuit with thicker metal lines on lower metallization layer

Electromigration resistant standard cell device

Electromigration resistant standard cell device

Block level design method for heterogeneous PG-structure cells

Block level design method for heterogeneous PG-structure cells

Method, system, and storage medium of resource planning for designing semiconductor device

Method for triple-patterning friendly placement

Method, system and computer program product for generating layout for semiconductor device

Integrated circuit with thicker metal lines on lower metallization layer

Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects

Multiple driver pin integrated circuit structure

Leakage analysis on semiconductor device

Standard cell design with dummy padding

Block level design method for heterogeneous PG-structure cells

Block level design method for heterogeneous PG-structure cells

Method, system, and storage medium of resource planning for designing semiconductor device

Cell placement site optimization

Constrained cell placement

Multiple patterning method and system for implementing the method

Method, system, and storage medium of resource planning for designing semiconductor device

Constrained cell placement

System and method of verifying slanted layout components

Integrated circuit with thicker metal lines on lower metallization layer

System and method of verifying slanted layout components

Semiconductor apparatus including uncrowned and crowned cells and method of making

TAIWAN SEMICONDUCTOR MFG

Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed

Layout re-decomposition for multiple patterning layouts

Double patterning technology (DPT) layout routing

Generating database for cells routable in pin layer

Systems and methods for designing layouts for semiconductor device fabrication

Reusable cut mask for multiple layers

Layout optimization for integrated design

CHEN HUANG-YU

Cell layout for multiple patterning technology

Routing system and method for double patterning technology

Method and apparatus for achieving multiple patterning technology compliant design layout

Method and system for replacing a pattern in a layout

Double patterning technology using single-patterning-spacer-technique

LU LEE-CHUNG

Non-hierarchical metal layers for integrated circuits

Methods for cell boundary isolation in double patterning design

System and method for on-chip-variation analysis

Electromigration resistant standard cell device

CHANG SHIH-MING

Semiconductor device with self-aligned interconnects and blocking portions

Semiconductor device with self-aligned interconnects

LIN HUNG LUNG

Tool and method for eliminating multi-patterning conflicts

HOU YUNG-CHIN

Integrated circuit design using DFM-enhanced architecture