Inventor
BROFMAN PETER J
US31 patents
⚠️ This page may combine multiple inventors who share the name “BROFMAN PETER J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
29 patentsUS6258625B1Jul 10, 2001
Method of interconnecting electronic components using a plurality of conductive studs
IBM243 citations99
US6270363B1Aug 7, 2001
Z-axis compressible polymer with fine metal matrix suspension
IBM105 citations98
US6878608B2Apr 12, 2005
Method of manufacture of silicon based package
IBM54 citations96
US6283359B1Sep 4, 2001
Method for enhancing fatigue life of ball grid arrays
IBM53 citations96
US5968670AOct 19, 1999
Enhanced ceramic ball grid array using in-situ solder stretch with spring
IBM63 citations96
US7709951B2May 4, 2010
Thermal pillow
IBM27 citations92
US6278184B1Aug 21, 2001
Solder disc connection
IBM35 citations92
US6253986B1Jul 3, 2001
Solder disc connection
IBM25 citations92
US6218629B1Apr 17, 2001
Module with metal-ion matrix induced dendrites for interconnection
IBM18 citations92
US6158644ADec 12, 2000
Method for enhancing fatigue life of ball grid arrays
IBM43 citations92
US6070321AJun 6, 2000
Solder disc connection
IBM20 citations92
US5975409ANov 2, 1999
Ceramic ball grid array using in-situ solder stretch
IBM36 citations92
US5964396AOct 12, 1999
Enhanced ceramic ball grid array using in-situ solder stretch with clip
IBM36 citations92
US5284286AFeb 8, 1994
Porous metal block for removing solder or braze from a substate and a process for making the same
IBM31 citations92
US5219520AJun 15, 1993
Process of making a porous metal block for removing solder or braze
IBM24 citations92
US6220499B1Apr 24, 2001
Method for assembling a chip carrier to a semiconductor device
IBM30 citations91
US5831810ANov 3, 1998
Electronic component package with decoupling capacitors completely within die receiving cavity of substrate
IBM41 citations88
US9698072B2Jul 4, 2017
Low-stress dual underfill packaging
IBM8 citations83
US7733655B2Jun 8, 2010
Lid edge capping load
IBM11 citations81
US6984792B2Jan 10, 2006
Dielectric interposer for chip to substrate soldering
IBM9 citations74
US6548909B2Apr 15, 2003
Method of interconnecting electronic components using a plurality of conductive studs
IBM11 citations74
US9373559B2Jun 21, 2016
Low-stress dual underfill packaging
IBM3 citations72
US6657313B1Dec 2, 2003
Dielectric interposer for chip to substrate soldering
IBM7 citations71
US8978960B2Mar 17, 2015
Flip chip assembly apparatus employing a warpage-suppressor assembly
IBM2 citations63
US7875502B2Jan 25, 2011
Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
IBM5 citations62
US6584684B2Jul 1, 2003
Method for assembling a carrier and a semiconductor device
IBM3 citations62
US6016947AJan 25, 2000
Non-destructive low melt test for off-composition solder
IBM6 citations57
US7732932B2Jun 8, 2010
Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
IBM1 citations52
US8910853B2Dec 16, 2014
Additives for grain fragmentation in Pb-free Sn-based solder
IBM0 citations51