Inventor

CAO JOSEPH JUN

US27 patents

⚠️ This page may combine multiple inventors who share the name “CAO JOSEPH JUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAO JOSEPH JUN

MARVELL INT LTD

Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level

Providing error checking and correcting (ECC) capability for memory

Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers

Universal adaptive voltage scaling system

Adaptive voltage scaling using a delay line

Providing error correcting code (ECC) capability for memory

Timing-budget-based quality-of-service control for a system-on-chip

Method for inter-chip and intra-chip addressing using port identifiers and address mapping

Adaptive voltage scaling using a delay line

Adaptive voltage scaling using a delay line

System and methods for storing data encoded with error information in a storage medium

System and method for accessing distinct regions of memory using multiple mapping modes, each of the mapping modes having a predetermined order of dimensions for a respective region of the memory

Universal adaptive voltage scaling system

Systems and methods for command execution order control in electronic systems

Apparatus and method for accessing non-overlapping portions of memory according to respective orders of dimensions

Adaptive voltage scaling using a delay line

System and methods for storing data encoded with error information in a storage medium

MARVELL WORLD TRADE LTD

Systems and methods for DQS gating

Providing low-latency error correcting code capability for memory

Chip-to-chip communications

System and method for automatic DQS gating based on counter signal

Systems and methods for dynamically determining a priority for a queue of commands

Systems and methods for dynamic priority control

Tunneling transaction packets

ZHU JUN

System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device

System and method for mixed-mode SDRAM address mapping

Variable length arbitration