Inventor

WEI ANDY C

US39 patents

⚠️ This page may combine multiple inventors who share the name “WEI ANDY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEI ANDY C

GLOBALFOUNDRIES INC

Methods of forming isolation structures and fins on a FinFET semiconductor device

Methods of forming nanowire devices with spacers and the resulting devices

Replacement metal gate diffusion break formation

Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices

Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device

Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins

Integrated circuits with dual silicide contacts and methods for fabricating same

Methods of forming nanowire devices with doped extension regions and the resulting devices

Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor products

Methods of forming contacts to source/drain regions of FinFET devices

Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark

Methods of forming finfet devices with a shared gate structure

Methods of forming a finfet semiconductor device with undoped fins

Integrated circuits with dual silicide contacts and methods for fabricating same

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices

Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines

Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same

Methods for fabricating stressed MOS devices

Methods of forming a FinFET semiconductor device with undoped fins

Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark

Self-aligned via process flow

ADVANCED MICRO DEVICES INC

Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate

Fully-depleted SOI device

Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same

Doped spacer liner for improved transistor performance

Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control

Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same

Biased, triple-well fully depleted SOI structure, and various methods of making and operating same

Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions

Biased, triple-well fully depleted SOI structure

SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate

Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same

Transistors with controllable threshold voltages, and various methods of making and operating same

WEI ANDY C

Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates

Methods for fabricating integrated circuits

Dual work function FinFET structures and methods for fabricating the same

FinFET structure with multiple workfunctions and method for fabricating the same

XIE RUILONG

Semiconductor devices having improved gate height uniformity and methods for fabricating same

PRINDLE CHRIS M

Dry etch polysilicon removal for replacement gates