Inventor
JIANG ZHE-WEI
TW21 patents
⚠️ This page may combine multiple inventors who share the name “JIANG ZHE-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
16 patentsUS9536032B2Jan 3, 2017
Method and system of layout placement based on multilayer gridlines
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations84
US11531802B2Dec 20, 2022
Layout context-based cell timing characterization
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations83
US10691849B2Jun 23, 2020
Metal cut optimization for standard cells
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations83
US10943050B2Mar 9, 2021
Capacitive isolation structure insert for reversed signals
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US9626472B2Apr 18, 2017
Method and system of forming layout design
TAIWAN SEMICONDUCTOR MFG CO LTD6 citations73
US11853676B2Dec 26, 2023
Layout context-based cell timing characterization
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US11030368B2Jun 8, 2021
Metal cut optimization for standard cells
TAIWAN SEMICONDUCTOR MFG CO LTD3 citations72
US12210811B2Jan 28, 2025
Layout context-based cell timing characterization
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12106033B2Oct 1, 2024
Metal cut optimization for standard cells
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12073162B2Aug 27, 2024
Capacitive isolation structure insert for reversed signals
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11734481B2Aug 22, 2023
Metal cut optimization for standard cells
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11526649B2Dec 13, 2022
Capacitive isolation structure insert for reversed signals
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations62
US11907633B2Feb 20, 2024
Layout for integrated circuit and the integrated circuit
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11494543B2Nov 8, 2022
Layout for integrated circuit and the integrated circuit
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US10685162B2Jun 16, 2020
Layout for integrated circuit and the integrated circuit
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US10163883B2Dec 25, 2018
Layout method for integrated circuit and layout of the integrated circuit
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
TAIWAN SEMICONDUCTOR MFG
3 patentsUS8826212B2Sep 2, 2014
Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed
TAIWAN SEMICONDUCTOR MFG112 citations97
US9058462B2Jun 16, 2015
System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)
TAIWAN SEMICONDUCTOR MFG7 citations82
US8356262B1Jan 15, 2013
Cell architecture and method
TAIWAN SEMICONDUCTOR MFG5 citations73